Disclosed are a method of manufacturing a microstructure array that includes preparing a mold having a concave micro pattern array in which a plurality of concave micro patterns are arranged, preparing a perovskite precursor solution including a perovskite precursor and a hydrophilic polymer, coating the perovskite precursor solution on a substrate, disposing the mold on the perovskite precursor solution to confine the perovskite precursor solution in the plurality of concave micro patterns, obtaining a composite of perovskite nanocrystals and the hydrophilic polymer from the perovskite precursor solution in the plurality of concave micro patterns, and, and removing the mold to form a microstructure array in which a plurality of microstructures including a composite of the perovskite nanocrystals and the hydrophilic polymer are arranged, a microstructure array, a micro light emitting diode including the same, and a manufacturing method thereof, and a display device.

A solar cell includes a first substrate, a first hole transport layer, a first photoelectric conversion layer containing a perovskite compound, and a second photoelectric conversion layer containing a photoelectric conversion material in this order. A band gap of the perovskite compound is greater than a band gap of the photoelectric conversion material. With respect to an absorption wavelength of the first photoelectric conversion layer 3, a refractive index n.sub.A of the first hole transport layer 2 satisfies refractive index of the first substrate≤n.sub.A≤refractive index of the first photoelectric conversion layer. Further, with respect to a transmission wavelength of the first photoelectric conversion layer 3 and an absorption wavelength of the second photoelectric conversion layer 5, a refractive index n.sub.B of the first hole transport layer 2 satisfies refractive index of the first substrate≤n.sub.B≤refractive index of the first photoelectric conversion layer.

An electronic device including an electronic unit and a functional unit is provided. The electronic unit includes a substrate, a plurality of semiconductor components, and a cover layer. The substrate has a plurality of first side surfaces. The semiconductor components are disposed on the substrate. The cover layer is disposed on the semiconductor components and has a plurality of second side surfaces. The functional unit is disposed on at least one of at least one of the first side surfaces and at least one of the second side surfaces.

The present disclosure relates to a wafer, a manufacturing method thereof, and a semiconductor device. The wafer manufacturing method includes: providing a wafer having a scribe lane for die cutting. A plurality of scribe-lane through-silicon-vias is formed at the scribe lane, and the scribe-lane through-silicon-vias are filled with a protective material to form the scribe lane. Through the technique of forming through-silicon vias at the scribe lane and filling them with protective materials, performing cutting along the line of the scribe-lane through-silicon-vias during wafer scribing, the cutting stress is reduced so and damage to the die area is prevented. The scribe-lane through-silicon-vias can effectively reduce the scribe lane width, which is conducive to miniaturizing the scribe lane and improving the effective utilization of wafers.

An electronic element mounting substrate includes a first substrate that has a first main surface, has a rectangular shape, and has a mounting portion for an electronic element on the first main surface, and a second substrate that is located on a second main surface opposite to the first main surface, is made of a carbon material, has a rectangular shape, has a third main surface facing the second main surface and a fourth main surface opposite to the third main surface, in which the third main surface or the fourth main surface has heat conduction in a longitudinal direction greater than heat conduction in a direction perpendicular to the longitudinal direction, and that has a recessed portion on the fourth main surface.

A module includes a substrate, which has a polygonal shape in a plan view, an electronic component and an electronic component, which are mounted on a main surface of the substrate, and side electrodes, which are provided on at least two side surfaces of a plurality of side surfaces that form the polygonal shape of the substrate. A conductor film coupled to the electronic component and a conductor film coupled to the electronic component are provided on the substrate. The conductor film extends to reach a side surface of the at least two side surfaces to be coupled to a side electrode provided on the side surface. The conductor film extends to reach a side surface of the at least two side surfaces, which is different from the side surface, to be coupled to a side electrode provided on the side surface.

A module includes: a substrate having a first face; a plurality of components mounted on the first face; a resin film that covers the plurality of components along contours of the plurality of components and also covers a part of the first face; and a shield film formed to overlap the resin film. The first face is provided with a ground electrode. The resin film has an opening, and the shield film is connected to the ground electrode via the opening.

A solar cell includes a first substrate, a first electrode layer, a first electron transport layer, a first photoelectric conversion layer, a first hole transport layer, a second electrode layer, a third electrode layer, a second electron transport layer, a second photoelectric conversion layer, a second hole transport layer, a fourth electrode layer, and a second substrate that are disposed in the order stated. The first photoelectric conversion layer includes a first perovskite compound, and the second photoelectric conversion layer includes a second perovskite compound. The first perovskite compound has a bandgap greater than a bandgap of the second perovskite compound.

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.

An electronic component module includes a plurality of components including a terminal and placed along a plane, a frame substrate supporting at least some components among the plurality of components, a sealing resin portion sealing the plurality of components and the frame substrate, and a shield layer covering an outer surface of the sealing resin portion. The frame substrate includes an insulating layer, a ground layer, and a ground bump electrically connected to the ground layer, and also an opening supporting a portion other than solder bumps of bump components, and the ground layer of the frame substrate is exposed to a side surface of the frame substrate and is electrically connected to the shield layer. The terminal of the plurality of components and the ground bump are exposed while protruding from a plane of the sealing resin portion and are used as mounting terminals of the electronic component module.