22In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.

A nonvolatile memory device includes a substrate; a memory cell array formed on the substrate in a vertically stacked structure; and a row decoder configured to supply a row line voltage to the memory cell array, the row decoder including a plurality of pass transistors. The row line voltage is supplied through a plurality of row lines connecting the pass transistors to the memory cell array. Each of the row lines includes a wiring line parallel with a main surface of the substrate and a contact perpendicular to the main surface of the substrate. The wiring line of at least one row line among the row lines includes a plurality of conductive lines.

A semiconductor device according to an embodiment includes first and second chips, and a first conductor. The first chip includes a first substrate, a first circuit and a first joint metal. The first circuit is provided on the first substrate. The first joint metal is connected to the first circuit. The second chip includes a second substrate, a second circuit, and a second joint metal. The second substrate includes P-type and N-type well regions. The second circuit is provided on the second substrate and includes a first transistor. The second joint metal is connected to the second circuit and the first joint metal. The first conductor is connected to the N-type well region from a top region of the second chip. The P-type well region is arranged between a gate electrode of the first transistor and the N-type well region.

Various embodiments of the present application are directed towards a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory device, as well as a method for forming the MFMIS memory device. According to some embodiments of the MFMIS memory device, a first source/drain region and a second source/drain region are vertically stacked. An internal gate electrode and a semiconductor channel overlie the first source/drain region and underlie the second source/drain region. The semiconductor channel extends from the first source/drain region to the second source/drain region, and the internal gate electrode is electrically floating. A gate dielectric layer is between and borders the internal gate electrode and the semiconductor channel. A control gate electrode is on an opposite side of the internal gate electrode as the semiconductor channel and is uncovered by the second source/drain region. A ferroelectric layer is between and borders the control gate electrode and the internal gate electrode.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.

A semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes conductive layers and insulating layers alternately stacked. The memory strings penetrate the stack along a first direction. Each of the memory strings includes a first conductive pillar, a second conductive pillar, a channel layer and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction, respectively, and electrically isolated to each other. The channel layer extends along the first direction. The channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer.

Embodiments provide a semiconductor device capable of being highly integrated.

A semiconductor device includes a semiconductor substrate, a first insulating layer formed toward an inside of a semiconductor substrate from a main surface of the semiconductor substrate, and a transistor formed on the first insulating layer. the transistor has a first semiconductor layer formed on the first insulating layer to be insulated from the semiconductor substrate, a second insulating layer provided on a second region among of a first region, the second region, and a third region sequentially arranged in a first direction along the main surface of the first semiconductor layer, and a first conductive layer provided on the second insulating layer. a first contact is connected to the first region of the first semiconductor layer, a second contact is connected to the third region of the first semiconductor layer, and a third contact is connected to the first conductive layer.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.

The disclosed technology relates generally to semiconductor memory devices, and more particularly to three-dimensional (3D) ferroelectric memory devices, methods of fabricating 3D ferroelectric memory devices, and methods of conditioning 3D ferroelectric memory devices. The 3D ferroelectric memory device exploits programmed memory cells as selector devices. In one aspect, a 3D ferroelectric memory device comprises a stack comprising a plurality of gate electrode layers and spacer layers, which are alternatingly arranged. The 3D ferroelectric memory device additionally comprises a semiconductor channel extending through the stack and a ferroelectric layer arranged between the gate electrode layers and the semiconductor channel. The gate electrode layers form, in combination with the channel and the ferroelectric layer, a string of ferroelectric transistors, wherein each ferroelectric transistor is associated with one cell of the memory device. The first ferroelectric transistor and the last ferroelectric transistor in the string have a lower threshold voltage than the other ferroelectric transistors.

A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.