The present invention generally relates to nanoscale wires and, in particular, to nanoscale wires with heterojunctions, such as tip-localized homo- or heterojunctions. In one aspect, the nanoscale wire may include a core, an inner shell surrounding the core, and an outer shell surrounding the inner shell. The outer shell may also contact the core, e.g., at an end portion of the nanoscale wire. In some cases, such nanoscale wires may be used as electrical devices. For example a p-n junction may be created where the inner shell is electrically insulating, and the core and the outer shell are p-doped and n-doped. Other aspects of the present invention generally relate to methods of making or using such nanoscale wires, devices, or kits including such nanoscale wires, or the like.

According to another embodiment, a method of forming a transistor is provided. The method includes the following operations: providing a substrate; providing a source over the substrate; providing a channel connected to the source; providing a drain connected to the channel; providing a gate insulator adjacent to the channel; providing a gate adjacent to the gate insulator; providing a first interlayer dielectric between the source and the gate; and providing a second interlayer dielectric between the drain and the gate, wherein at least one of the formation of the source, the drain, and the channel includes about 20-95 atomic percent of Sn.

A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

A Schottky barrier diode includes a graphene nanoribbon, a first electrode connected to one end of the graphene nanoribbon, and a second electrode connected to the other end of the graphene nanoribbon. The graphene nanoribbon includes a first part and a second part which are connected in the length direction of the graphene nanoribbon and which differ in electronic state. For example, edges of the first part in a length direction of the graphene nanoribbon are terminated with a first modifying group and edges of the second part in the length direction of the graphene nanoribbon are terminated with a second modifying group.

Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first stack of semiconductor layers including a first doped Si layer, a first channel layer, and a second doped Si layer, respectively, on a Si substrate; forming a second stack including a first doped SiGe layer, a second channel layer, and a second doped SiGe layer, respectively, on the first stack; forming a vertical nanowire structure by directional etching, along a three-dimensional plane, the second and first stacks, respectively, down to an upper surface of the Si substrate; forming lower S/D regions and a lower gate-stack surrounding the first stack; forming upper S/D regions and an upper gate-stack surrounding the second stack; and forming contacts to the lower S/D regions, a first gate electrode, an upper S/D region, an upper gate electrode, and the second doped SiGe layer.

The tunneling channel of a field effect transistor comprising a plurality of tunneling elements contacting a channel substrate. Applying a source-drain voltage of greater than a turn-on voltage produces a source-drain current of greater than about 10 pA. Applying a source-drain voltage of less than a turn-on voltage produces a source-drain current of less than about 10 pA. The turn-on voltage at room temperature is between about 0.1V and about 40V.

An electronic substrate or interposer comprising nanoporous films, such as anodic aluminum oxide, containing vertically etched openings (“vias”) that are filled with a conductive material, forming a high density collection of vertically oriented vias that conduct electricity from one side of the substrate to the other.

A semiconductor device includes first and second nanowire structures, first and second annular hafnium oxide layers, first and second annular cap layers, and first and second metal gate electrodes. The first and second nanowire structures are suspended over a substrate and respectively have an n-channel region and a p-channel region. The first and second annular hafnium oxide layers encircle the n-channel region and the p-channel region, respectively. The first and second annular cap layers encircle the first and second annular hafnium oxide layers, respectively. The first and second annular cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes encircle the first and second annular cap layers, respectively. The first and second metal gate electrodes have a same metal composition.

An apparatus for measuring electrical potentials of a liquid sample includes at least one field effect transistor having a source, a drain, and a gate, a substrate, and at least two intersecting nanowires of semiconductive material arranged on the substrate, each having a source and drain contact as a field effect transistor and a voltage applicator configured to apply a voltage between the respective source and drain contact. The cross section of the two nanowires has a shape of a triangle or a trapezium. A voltage applicator configured to apply a voltage to the substrate are arranged on the substrate. The nanowires are electrically insulated at least against the sample by a dielectric layer along their surface having a layer thickness between 5 and 40 nm, and at least one impurity is arranged in the dielectric layer as a bearing point which is capable of capturing charge carriers.

An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.