A SiC epitaxial wafer of the present invention includes a SiC single crystal substrate, and a high concentration layer that is provided on the SiC single crystal substrate and has an average value of an n-type doping concentration of 1×10.sup.18/cm.sup.3 or more and 1×10.sup.19/cm.sup.3 or less, and in-plane uniformity of the doping concentration of 30% or less.

A GaN diode EMP arrestor exhibits breakdown in <10 ns at reverse-bias voltage >20 kV. Additionally, the arrestor exhibits avalanche ruggedness at 1 kA/cm.sup.2 in a 1 mm.sup.2 device (i.e. 10 A absolute current) over a period of 500 ns following the onset of breakdown. Finally, the specific on-resistance in the forward direction is <20 mΩ cm.sup.2.

A semiconductor field-effect transistor, a power amplifier comprising the same and a manufacturing method thereof are provided herein. The semiconductor field-effect transistor contains an n-type doped layer arranged close to the edge of the two-dimensional electron gas area in a channel layer; said n-type doped layer is arranged to adjust the distribution of electron concentration in the transistor, and to improve the RF linearity of the overall component; thereby not only the threshold voltage can be controlled through the adjustment of the charge, but the contact and series resistance can also be reduced.

A semiconductor device includes trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate, a first conductivity type lower surface region provided in a part of a lower surface of the semiconductor substrate, a second conductivity type base region provided on the upper surface side, a first conductivity type first region disposed between the base region and the lower surface region, a first conductivity type upper surface region provided on an upper surface of the semiconductor substrate, and a second conductivity type bottom region disposed continuously in the first direction to be in contact with bottom portions of the trench portions. In a cross section along the first direction and perpendicular to the upper and lower surfaces and passing through the lower surface region, one end portion of the bottom region in the first direction locates directly above the lower surface region.

A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 μm. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode.

A semiconductor structure and a manufacturing method thereof are provided in the present application provides. The semiconductor structure includes a substrate and a heterojunction structure located on the substrate. The heterojunction structure includes a channel layer and a barrier layer located on the channel layer. The channel layer includes at least one n-type doped layer. The manufacturing method of the semiconductor structure includes: providing a substrate; forming a heterojunction structure on the substrate, where forming the heterojunction structure includes: forming a channel layer on the substrate, doping the channel layer to form an n-type doped layer; forming a barrier layer on the channel layer; forming a gate electrode, a source electrode and a drain electrode, the gate electrode is located on the heterojunction structure, and the source electrode and the drain electrode are located on two sides of the grid electrode, separately.

A semiconductor device includes an edge terminal structure portion provided between the active portion and an end portion of the semiconductor substrate on an upper surface of the semiconductor substrate, in which the edge terminal structure portion has a first high concentration region of the first conductivity type which has a donor concentration higher than a doping concentration of the bulk donor in a region between the upper surface and a lower surface of the semiconductor substrate, an upper surface of the first high concentration region is located on an upper surface side of the semiconductor substrate, and a lower surface of the first high concentration region is located on a lower surface side of the semiconductor substrate.

A semiconductor device having metamorphic high electron mobility transistor (HEMT)-heterojunction bipolar transistor (HBT) integration on a semiconductor substrate. An example semiconductor device generally includes a semiconductor substrate, a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium, and a HEMT disposed above the semiconductor substrate and comprising indium.

A silicon carbide semiconductor substrate includes an epitaxial layer. A difference of a donor concentration and an acceptor concentration of the epitaxial layer is within a range from 1×10.sup.14/cm.sup.3 to 1×10.sup.15/cm.sup.3. Further, the donor concentration and the acceptor concentration of the epitaxial layer are a concentration unaffected by an impurity inside epitaxial growth equipment.

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.