H01L29/66053

SiC epitaxial wafer, semiconductor device, and power converter

A SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer disposed on the SiC substrate. The SiC epitaxial layer includes a high carrier concentration layer and two low carrier concentration layers having lower carrier concentration than the high carrier concentration layer, and being in contact with a top surface and a bottom surface of the high carrier concentration layer to sandwich the high carrier concentration layer. A difference in carrier concentration between the high carrier concentration layer and the low carrier concentration layers is 5×10.sup.14/cm.sup.3 or more and 2×10.sup.16/cm.sup.3 or less.

Semiconductor device having a ferroelectric gate stack

A semiconductor device includes a SiC substrate and a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate. The gate dielectric stack includes a ferroelectric insulator. The transistor has a specified operating temperature range, and the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor. A corresponding method of producing the semiconductor device is also described.

Methods of Forming Semiconductor Devices in a Layer of Epitaxial Silicon Carbide

A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR
20220302261 · 2022-09-22 · ·

A semiconductor device of embodiments includes: a silicon carbide layer having a first face having an off-angle of 0° or more and 8° or less with respect to a {0001}face and a second face opposite to the first face, having a 4H-SiC crystal structure, and including a first silicon carbide region of p-type, a second silicon carbide region of n-type between the first silicon carbide region and the first face, and a third silicon carbide region between the first silicon carbide region and the first face and containing oxygen, the second silicon carbide region disposed between the third silicon carbide region and the first face; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration of 1×10.sup.21 cm.sup.−3 or more.

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
20220262905 · 2022-08-18 · ·

A silicon carbide semiconductor device, including a semiconductor substrate containing silicon carbide, a bonding wire, and a surface electrode of an aluminum alloy containing silicon, the surface electrode being provided on a surface of the semiconductor substrate, and having a joint portion to which the bonding wire is bonded. The surface electrode has a plurality of silicon nodules formed therein, which include a number of the silicon nodules formed in the joint portion. One of the number of the silicon nodules is of a dendrite structure, and is included at an area percentage of at least 10% relative to a total area of the number of the silicon nodules in the joint portion.

SiC SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREFOR
20220102502 · 2022-03-31 ·

A method for manufacturing an SiC semiconductor device includes a step of setting, on a main surface of an SiC wafer, a scheduled cutting line that demarcates a plurality of chip regions including a first chip region in which a functional device is formed and a second chip region in which a monitor pattern for performing process control of the first chip region is formed, a step of forming, on the main surface, a plurality of main surface electrodes respectively covering the chip regions such as to expose the scheduled cutting line and respectively forming a portion of the functional device and a portion of the monitor pattern, a step of irradiating laser light to the scheduled cutting line and forming a modified region, and a step of cleaving the SiC wafer with the modified region as a starting point.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
20220102485 · 2022-03-31 ·

A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.

MANUFACTURING METHOD OF AN ELEMENT OF AN ELECTRONIC DEVICE HAVING IMPROVED RELIABILITY, AND RELATED ELEMENT, ELECTRONIC DEVICE AND ELECTRONIC APPARATUS

A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body.

Methods of Re-using a Silicon Carbide Substrate

A method includes providing a layer of porous silicon carbide supported by a silicon carbide substrate, providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide, forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide, and separating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. Additional methods are described.

Solid Body and Multi-Component Arrangement

A solid body is disclosed. The solid body includes: a detachment plane in an interior space of the solid body, the detachment plane including laser radiation-induced modifications; and a region including layers and/or components. A multi-component arrangement is also disclosed. The multi-component arrangement includes: a solid-body layer including more than 50% SiC and modifications or modification components generating pressure tensions in a region of a first surface, the modifications being amorphized components of the solid-body layer, the modifications being spaced closer to the first surface than to a second surface opposite the first surface, the first surface being essentially level; and a metal layer on the first surface of the solid-body layer.