Low-flow tungsten chemical vapor deposition (CVD) techniques described herein provide substantially uniform deposition of tungsten on a semiconductor substrate. In some implementations, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD). This reduces the likelihood of defect formation in the tungsten layer while increasing the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates).

A device includes a substrate including an active region, a gate stack over the active region, and a hard mask over the gate stack. The hard mask includes a capping layer, a buttress layer extending along sidewalls and a bottom of the capping layer, and a liner layer extending along sidewalls and a bottom of the buttress layer. The buttress layer includes a metal oxide material or a metal nitride material.

A semiconductor device includes: a pair of wire patterns configured to extend in a first direction and formed on a substrate to be spaced apart from each other in a second direction, the pair of wire patterns disposed closest to each other in the second direction; a gate electrode configured to extend in the second direction on the substrate, the gate electrode configured to surround the wire patterns; and first isolation layers configured to extend in the first direction between the substrate and the gate electrode and formed to be spaced apart from each other in the second direction, the first isolation layers overlapping the pair of wire patterns in a third direction perpendicular to the first and second directions.

A method used in forming an array of memory cells comprises forming lines of top-source/drain-region material, bottom-source/drain-region material, and channel-region material vertically there-between in rows in a first direction. The lines are spaced from one another in a second direction. The top-source/drain-region material, bottom-source/drain-region material, and channel-region material have respective opposing sides. The channel-region material on its opposing sides is laterally recessed in the second direction relative to the top-source/drain-region material and the bottom-source/drain-region material on their opposing sides to form a pair of lateral recesses in the opposing sides of the channel-region material in individual of the rows. After the pair of lateral recesses are formed, the lines of the top-source/drain-region material, the channel-region material, and the bottom-source/drain-region material are patterned in the second direction to comprise pillars of individual transistors. Rows of wordlines are formed in the first direction that individually are operatively aside the channel-region material of individual of the pillars in the pairs of lateral recesses and that interconnect the transistors in that individual row. Other embodiments, including structure independent of method, are disclosed.

A method includes depositing an interlayer dielectric (ILD) over a source/drain region, implanting impurities into a portion of the ILD, recessing the portion of the ILD to form a trench, forming spacers on sidewalls of the trench, the spacers including a spacer material, forming a source/drain contact in the trench and removing the spacers and the portion of the ILD with an etching process to form an air-gap, the air-gap disposed under and along sidewalls of the source/drain contact, where the etching process selectively etches the spacer material and the impurity.

A forksheet transistor device includes a dual dielectric pillar that includes a first dielectric and a second dielectric that is different from the first dielectric. The dual dielectric pillar physically separates pFET elements from nFET elements. For example, the first dielectric physically separates a pFET gate from a nFET gate while the second dielectric physically separates a pFET source/drain region from a nFET source drain region. When it is advantageous to electrically connect the pFET gate and the nFET gate, the first dielectric may be etched selective to the second dielectric to form a gate connector trench within the dual dielectric pillar. Subsequently, an electrically conductive gate connector strap may be formed within the gate connector trench to electrically connect the pFET gate and the nFET gate.

A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.