A method for forming an integrated circuit device is provided. The method includes forming a transistor over a frontside of a substrate; forming an interconnect structure over the transistor; depositing a first transition metal layer over the interconnect structure; performing a plasma treatment to turn the first transition metal layer into a first transition metal dichalcogenide layer; forming a dielectric layer over the first transition metal dichalcogenide layer; forming a first gate electrode over the dielectric layer and a first portion of the first transition metal dichalcogenide layer; and forming a first source contact and a first drain contact respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer, the first portion of the first transition metal dichalcogenide layer being between the second and third portions of the first transition metal dichalcogenide layers.

A device comprises a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend in a first direction above a substrate and arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are respectively on opposite sides of the gate structure.

A transistor includes a gate structure, a channel layer underlying the gate structure and comprising a two-dimensional (2D) material, source/drain contacts laterally spaced apart from the gate structure and disposed laterally next to the channel layer, and a spacer laterally interposed between the gate structure and the source/drain contacts. A semiconductor device and a semiconductor structure are also provided.

A transistor comprises a pair of source/drain regions having a channel region there-between. A transistor gate construction is operatively proximate the channel region. The channel region comprises a direction of current flow there-through between the pair of source/drain regions. The channel region comprises at least one of GaP, GaN, and GaAs extending all along the current-flow direction. Each of the source/drain regions comprises at least one of GaP, GaN, and GaAs extending completely through the respective source/drain region orthogonal to the current-flow direction. The at least one of the GaP, the GaN, and the GaAs of the respective source/drain region is directly against the at least one of the GaP, the GaN, and the GaAs of the channel region. Each of the source/drain regions comprises at least one of elemental silicon and metal material extending completely through the respective source/drain region orthogonal to the current-flow direction. Other embodiments are disclosed.

A semiconductor device is provided and includes a substrate and a stack on the substrate. The stack includes plural active layers that are vertically stacked and spaced apart from each other, and plural gate electrodes that are on the active layers, respectively, and vertically stacked. Each active layer includes a channel layer under a corresponding one of the gate electrodes, and a source/drain layer disposed at a side of the channel layer and electrically connected to the channel layer. The channel layer is made of a two-dimensional atomic layer of a first material.

Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.

The present disclosure provides a piezoelectric sensor, a pressure detecting device, their manufacturing methods and a detection method. The piezoelectric sensor comprises a thin film transistor located on a substrate and comprising an active layer, and a piezoelectric layer that is in contact with the active layer of the thin film transistor.

Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

Disclosed are an electronic device including a two-dimensional material, and a method of fabricating the electronic device. The electronic device may include a first metal layer including a transition metal, a second metal layer on the first metal layer and including gold (Au), and a two-dimensional material layer between the first metal layer and the second metal layer. The two-dimensional material layer may include a transition metal dichalcogenide (TMD). The two-dimensional material layer may be formed as a chalcogen element diffuses into the second metal layer and reacts with the transition metal of the first metal layer adjacent to the second metal layer.

According to another embodiment, a method of forming a transistor is provided. The method includes the following operations: providing a substrate; providing a source over the substrate; providing a channel connected to the source; providing a drain connected to the channel; providing a gate insulator adjacent to the channel; providing a gate adjacent to the gate insulator; providing a first interlayer dielectric between the source and the gate; and providing a second interlayer dielectric between the drain and the gate, wherein at least one of the formation of the source, the drain, and the channel includes about 20-95 atomic percent of Sn.