Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.

A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n.sup.+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n.sup.+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n.sup.+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET, Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

The present subject matter relates to an electrical programmable read only memory (EPROM) cell. The EPROM cell comprises a semiconductor substrate and a floating gate separated from the semiconductor substrate by a first dielectric layer. A control gate is capacitively coupled to the floating gate through a second dielectric layer disposed between the floating gate and the control gate. In an example, the EPROM cell further comprises a conductive gate connected to the floating gate, wherein the conductive gate is to leak charges from the floating gate in a predetermined leak time period.

A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.

A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Disclosed is a method of manufacturing a semiconductor device, including: forming a slacked structure including first material layers and second material layers alternately stacked on each other; forming a pillar passing through the stacked structure, the pillar including a protruding portion protruding above an uppermost surface of the stacked structure; forming a conductive layer surrounding the protruding portion of the pillar; and forming a conductive pattern in contact with the protruding portion of the pillar by oxidizing a surface of the conductive layer.