A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.

Semiconductor devices and associated fabrication methods are disclosed. In one disclosed approach a process for forming a semiconductor device is provided. The process includes: implanting a first region of semiconductor material using a first channeled implant with a first conductivity type; and implanting, after the first channeled implant, a second region of semiconductor material using a second channeled implant with a second conductivity type. The first channeled implant disrupts a crystal structure of the first region of semiconductor material and does not disrupt a crystal structure of the second region of semiconductor material.

A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.

A power SiC MOSFET with a built-in Schottky rectifier provides advantages of including a Schottky rectifier, such as avoiding bipolar degradation, while reducing a parasitic capacitive charge and related power losses, as well as system cost. A lateral built-in channel layer may enable lateral spacing of the MOSFET gate oxide from a high electric field at the Schottky contact, while also providing current limiting during short-circuit events.

The present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first n-type semiconductor layer, a p-type semiconductor layer, and a second n-type semiconductor layer which are stacked. A buried layer made of AlGaN is disposed in the first n-type semiconductor layer. A trench at least penetrates through the second n-type semiconductor layer and the p-type semiconductor layer. At least part of the buried layer is reserved below the trench. A gate electrode is in the trench. The method is used to manufacture this semiconductor structure.

The present application provides methods for manufacturing a vertical device. To begin with, a GaN-based semiconductor substrate (10) is etched from a front surface (10a) to form a trench (101). Then, a P-type semiconductor layer (11) and an N-type semiconductor layer (12) are sequentially formed on a bottom wall and side walls of the trench (101) and the front surface (10a) of the semiconductor substrate. The trench (101) is partially filled with the P-type semiconductor layer (11). Thereafter, the N-type semiconductor layer (12) and the P-type semiconductor layer (11) are planarized, and the P-type semiconductor layer (11) and the N-type semiconductor layer (12) in the trench (101) are retained. Next, a gate structure (13) is formed at a gate area of the front surface (10a) of the semiconductor substrate, a source electrode (14) is formed on two sides of the gate structure (13), and a drain electrode (15) is formed on a rear surface (10b) of the semiconductor substrate respectively. Etching the N-type semiconductor layer (12) and the P-type semiconductor layer (11) is avoided to make the gate structure (13), thereby avoiding that the control capability of the gate structure (13) deviates from a pre-designed control capability due to a difficulty in precise control over an etching depth. In this way, the performance of the vertical device can be precisely controlled through a manufacturing process.

A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 μm or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

A semiconductor device structure includes a region of semiconductor material comprising a first conductivity type, an active region, and a termination region. A first active trench structure is disposed in the active region, and a second active trench structure is disposed in the active region and laterally separated from the first active trench by an active mesa region having a first width. A first termination trench structure is disposed in the termination region and separated from the second active trench by a transition mesa region having a second width and a higher carrier charge than that of the active mesa region. In one example, the second width is greater than the first width to provide the higher carrier charge. In another example, the dopant concentration in the transition mesa region is higher than that in the active mesa region to provide the higher carrier charge. The semiconductor device structure exhibits improved device ruggedness including, for example, improve unclamped inductive switching (UIS) performance.

A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 μm or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.