A semiconductor test structure includes a field-effect transistor and a metal connection structure. The field-effect transistor includes a substrate with first doping type, a gate located on a surface of the substrate, and a source region with a second doping type and a drain region with the second doping type in the substrate, the source region and the drain region are located on two sides of the gate, respectively. The metal connection structure is connected with the gate; the metal connection structure forms a Schottky contact with the substrate.

A compound semiconductor has a high electron concentration of 5×10.sup.19 cm.sup.−3 or higher, exhibits an electron mobility of 46 cm.sup.2/V.Math.s or higher, and exhibits a low electric resistance, and thus is usable to produce a high performance semiconductor device. The present invention provides a group 13 nitride semiconductor of n-type conductivity that may be formed as a film on a substrate having a large area size at a temperature of room temperature to 700° C.

A compound semiconductor has a high electron concentration of 5×10.sup.19 cm.sup.−3 or higher, exhibits an electron mobility of 46 cm.sup.2/V.Math.s or higher, and exhibits a low electric resistance, and thus is usable to produce a high performance semiconductor device. The present invention provides a group 13 nitride semiconductor of n-type conductivity that may be formed as a film on a substrate having a large area size at a temperature of room temperature to 700° C.

A semiconductor die includes a semiconductor body, and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a plurality of sublayers that are stacked on the semiconductor body. Each of the sublayers comprises a respective stress in one or more directions, where the respective stresses of at least two of the sublayers are different. The sublayers may include a first stressor sublayer comprising first stress, and a second stressor sublayer comprising a second stress that at least partially compensates for the first stress in the one or more directions. Related devices and methods of fabrication are also discussed.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.

There is provided a nitride semiconductor laminate, including: a substrate; an electron transit layer provided on the substrate and containing a group III nitride semiconductor; and an electron supply layer provided on the electron transit layer and containing a group III nitride semiconductor, wherein a surface force A of the electron supply layer acting as an attractive force for attracting a probe and a surface of the electron supply layer when measured using the probe consisting of a glass sphere with a diameter of 1 mm covered with Cr, is stronger than a surface force B of Pt when measured under the same condition, and an absolute value |A−B| of a difference between them is 30 μN or more.

There is provided a nitride semiconductor laminate, including: a substrate; an electron transit layer provided on the substrate and containing a group III nitride semiconductor; and an electron supply layer provided on the electron transit layer and containing a group III nitride semiconductor, wherein a surface force A of the electron supply layer acting as an attractive force for attracting a probe and a surface of the electron supply layer when measured using the probe consisting of a glass sphere with a diameter of 1 mm covered with Cr, is stronger than a surface force B of Pt when measured under the same condition, and an absolute value |A−B| of a difference between them is 30 μN or more.

The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current.

The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current.