A display device is provided. The display device comprising: a substrate including a display area and a pad area, a first conductive layer disposed on the substrate and including a first signal line disposed in the display area, a buffer layer disposed on the first conductive layer, a semiconductor layer disposed on the buffer layer in the display area, a gate insulating film disposed on the semiconductor layer, a second conductive layer disposed on the gate insulating film and including a gate electrode overlapping the semiconductor layer in the display area, a first electrode of a transistor disposed to overlap one side of the semiconductor layer in the display area and connected to the first signal line through a contact hole penetrating through the buffer layer and the gate insulating film, and a second electrode of the transistor disposed to overlap the other side of the semiconductor layer in the display area, a first pad disposed on the buffer layer in the pad area and exposed by a pad opening, a first insulating layer disposed on the second conductive layer and the first pad, and a light emitting element disposed on the first insulating layer in the display area, wherein the first pad is formed of the first conductive layer or the second conductive layer.

A display device includes a scan write line configured to receive a scan write signal, a scan initialization line configured to receive a scan initialization signal, a sweep signal line configured to receive a sweep signal, a first data line configured to receive a first data voltage, a second data line configured to receive a second data voltage, and a subpixel connected to the scan write line, the scan initialization line, the sweep signal line, the first data line, and the second data line. The subpixel includes a light-emitting element, a first pixel driver including a first transistor configured to generate a control current according to the first data voltage of the first data line, and a second pixel driver including an eighth transistor configured to generate a driving current applied to the light-emitting element according to the second data voltage.

The present disclosure provides an electronic device including a substrate, a conductive pad, a chip and an insulating layer. The conductive pad is disposed on the substrate. The chip is disposed on the conductive pad. The insulating layer is disposed between the conductive pad and the chip, wherein the insulating layer includes an opening, and the chip is electrically connected to the conductive pad through the opening. An outline of the opening includes a plurality of curved corners in a normal direction of the substrate.

The present disclosure provides an electronic device including a substrate, a conductive pad, a chip and an insulating layer. The conductive pad is disposed on the substrate. The chip is disposed on the conductive pad. The insulating layer is disposed between the conductive pad and the chip, wherein the insulating layer includes an opening, and the chip is electrically connected to the conductive pad through the opening. An outline of the opening includes a plurality of curved corners in a normal direction of the substrate.

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

A pixel may include first and second electrodes spaced apart from each other along a first direction, first light emitting elements arranged along a second direction in a first area between the first electrode and the second electrode, and including a first end portion adjacent to the first electrode and a second end portion adjacent to the second electrode, a first contact electrode on the first end portions of the first light emitting elements, and including a transparent electrode layer, a second contact electrode on the second end portions of the first light emitting elements, and including a reflective electrode layer, a first bank pattern overlapping a portion of the first electrode beneath the first electrode, and a second bank pattern overlapping a portion of the second electrode beneath the second electrode, wherein the first and second bank patterns are spaced apart from the first area by different distances.

A display device includes a substrate including a pad area, a first conductive pattern disposed in the pad area on the substrate, an insulating layer disposed on the first conductive pattern and overlapping the first conductive pattern, second conductive patterns disposed on the insulating layer, spaced apart from each other, and contacting the first conductive pattern through contact holes formed in the insulating layer, and a third conductive pattern disposed on the second conductive patterns and contacting the insulating layer.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.