A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars.

A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars.

Embodiments may relate to a microelectronic package that includes a die, a thermal interface material (TIM) coupled with the die, and an integrated heat spreader (IHS) coupled with the TIM. The IHS may include a feature with a non-uniform cross-sectional profile that includes a thin point and a thick point as measured in a direction perpendicular to a face of the die to which the TIM is coupled. Other embodiments may be described or claimed.

A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

[Object] To provide a semiconductor protective film capable of suppressing a warpage of a semiconductor chip without impairing productivity and reliability, a semiconductor device including this, and a composite sheet. [Solving Means] A semiconductor protective film 10 according to an embodiment of the present invention includes a protective layer 11 formed of a non-conductive inorganic material and an adhesive layer 12 provided on one surface of the protective layer 11. The protective layer 11 includes at least a vitreous material and is typically formed of plate glass. Accordingly, a warpage of a semiconductor element as a protection target can be suppressed effectively.

The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material.

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.