A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.

A hybrid-integrated series/parallel-connected photovoltaic diode array employs 10s-to-100s of single-wavelength III-V compound semiconductor photodiodes in an array bonded onto a transparent optical plate through which the array is illuminated by monochromatic light. The power-by-light system receiver enables high-voltage, up to 1000s of volts, optical transmission of power to remote electrical systems in harsh environments.

A hybrid-integrated series/parallel-connected photovoltaic diode array employs 10s-to-100s of single-wavelength III-V compound semiconductor photodiodes in an array bonded onto a transparent optical plate through which the array is illuminated by monochromatic light. The power-by-light system receiver enables high-voltage, up to 1000s of volts, optical transmission of power to remote electrical systems in harsh environments.

The present disclosure provides glass, and a manufacturing method and a control method thereof. The glass includes a first glass layer, a plurality of transparent conductive strips and a second glass layer. The plurality of transparent conductive strips are between the first glass layer and the second glass layer, and are configured to generate heat when being supplied with power.

The present disclosure provides glass, and a manufacturing method and a control method thereof. The glass includes a first glass layer, a plurality of transparent conductive strips and a second glass layer. The plurality of transparent conductive strips are between the first glass layer and the second glass layer, and are configured to generate heat when being supplied with power.

An assembly for optical to electrical power conversion including a photodiode assembly having a substrate layer and an internal side, an antireflective layer, a heterojunction buffer layer adjacent the internal side; an active area positioned adjacent the heterojunction buffer layer, a plurality of n+ electrode regions and p+ electrode regions positioned adjacent the active area, and back-contacts configured to align with the n+ and p+ electrode regions. The active area converts photons from incoming light into liberated electron hole pairs. The heterojunction buffer layer prevents electrons and holes of the liberated electron hole pairs from moving toward the substrate layer. The plurality of electrode regions are configured in an alternating pattern with gaps between each n+ and p+ electrode region. The electrode regions receive and generate electrical current from migration of the electrons and the holes, provide electrical pathways for the electrical current, and provide thermal pathways to dissipate heat.

An assembly for optical to electrical power conversion including a photodiode assembly having a substrate layer and an internal side, an antireflective layer, a heterojunction buffer layer adjacent the internal side; an active area positioned adjacent the heterojunction buffer layer, a plurality of n+ electrode regions and p+ electrode regions positioned adjacent the active area, and back-contacts configured to align with the n+ and p+ electrode regions. The active area converts photons from incoming light into liberated electron hole pairs. The heterojunction buffer layer prevents electrons and holes of the liberated electron hole pairs from moving toward the substrate layer. The plurality of electrode regions are configured in an alternating pattern with gaps between each n+ and p+ electrode region. The electrode regions receive and generate electrical current from migration of the electrons and the holes, provide electrical pathways for the electrical current, and provide thermal pathways to dissipate heat.

A visibly transparent planar structure using a CPA scheme to boost the absorption of a multi-layer thin-film configuration, requiring no surface patterning, to overcome the intrinsic absorption limitation of the absorbing material. This is achieved in a multi-layer absorbing Fabry-Perot (FP) cavity, namely a thin-film amorphous silicon solar cell. Omni-resonance is achieved across a bandwidth of 80 nm in the near-infrared (NIR), thus increasing the effective absorption of the material, without modifying the material itself, enhancing it beyond its intrinsic absorption over a considerable spectral range. The apparatus achieved an increased external quantum efficiency (EQE) of 90% of the photocurrent generated in the 80 nm NIR region from 660 to 740 nm as compared to a bare solar cell. over the spectral range of interest.

A visibly transparent planar structure using a CPA scheme to boost the absorption of a multi-layer thin-film configuration, requiring no surface patterning, to overcome the intrinsic absorption limitation of the absorbing material. This is achieved in a multi-layer absorbing Fabry-Perot (FP) cavity, namely a thin-film amorphous silicon solar cell. Omni-resonance is achieved across a bandwidth of 80 nm in the near-infrared (NIR), thus increasing the effective absorption of the material, without modifying the material itself, enhancing it beyond its intrinsic absorption over a considerable spectral range. The apparatus achieved an increased external quantum efficiency (EQE) of 90% of the photocurrent generated in the 80 nm NIR region from 660 to 740 nm as compared to a bare solar cell. over the spectral range of interest.

Monolithic multi-throw diode switch structures are described. The monolithic multi-throw diode switches include a hybrid arrangement of diodes with different intrinsic regions. In one example, a method of manufacture of a monolithic multi-throw diode switch includes providing an intrinsic layer on an N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer to form a first PIN diode comprising a first effective intrinsic region of a first thickness, implanting a second P-type region to a second depth into the intrinsic layer to form a second PIN diode comprising a second effective intrinsic region of a second thickness, and forming at least one metal layer over the intrinsic layer to electrically couple the first PIN diode to a node between a common port and a first port of the switch.