A laser diode driver circuit is provided that has a loop including a laser diode, a drive capacitor for storing drive charge, and a switch element, a first inductor coupled in series with the laser diode, a parallel capacitor coupled in parallel with a series circuit composed of the laser diode and the first inductor, and a first diode coupled in parallel with the series circuit in opposite polarity to the laser diode.

A semiconductor laser including: an optical resonator that has a first compound semiconductor layer containing an n-type impurity, a second compound semiconductor layer containing a p-type impurity, and a light-emitting layer provided between the first compound semiconductor layer and the second compound semiconductor layer; and a pulse injection means that injects excitation energy for a sub-nanosecond duration into the optical resonator, wherein the optical resonator has a multi-section structure separated into at least one gain region and at least one absorption region, and the semiconductor laser generates optical pulses having a pulse width shorter than 2.5 times the photon lifetime in the optical resonator.

A driver circuit includes a fly capacitor with a first end and a second end. The driver circuit includes a laser diode having an anode and a cathode. The driver circuit is configured to operate in first and second operating states. The anode is coupled to the first end of the fly capacitor. In the first operating state, the cathode is coupled to a first voltage supply node, the first end of the fly capacitor is coupled to a second voltage supply node, and the second end of the fly capacitor is coupled to a first reference terminal. In the second operating state, the cathode is coupled to a second reference terminal and decoupled from the first voltage supply node, the first end of the fly capacitor is decoupled from the second voltage supply node, and the second end of the fly capacitor is coupled to a third reference terminal.

A surface emitting laser includes a first reflective layer, an active layer provided on the first reflective layer, and a second reflective layer provided on the active layer. The first reflective layer, the active layer, and the second reflective layer form a mesa, and the mesa has an electrically insulating region and an electrically conductive region. The electrically insulating region is positioned at a center portion of the mesa in a surface direction, and the electrically conductive region includes the first reflective layer, the active layer, and the second reflective layer and is positioned outside the electrically insulating region in such a manner as to surround the electrically insulating region.

A first conductive pattern (13) is provided on an upper surface of the submount (7). A GND pattern (9) is provided on a lower surface of the submount (7). A lower surface electrode (21) of a capacitor (3) is bonded to the first conductive pattern (13) with solder (22). An upper surface electrode (23) of the capacitor (3) is connected to a light emitting device (2). A terminating resistor (4) is connected to the first conductive pattern (13). The first conductive pattern (13) has a protruding portion (25) which protrudes outside from the capacitor (3) in planar view. A width of the protruding portion (25) is narrower than a width of the capacitor (3).

Methods, devices and systems are described for enabling a series-connected, single chip vertical-cavity surface-emitting laser (VCSEL) array. In one aspect, the single chip includes one or more non-conductive regions one the conductive layer to produce a plurality of electrically separate conductive regions. Each electrically separate region may have a plurality of VCSEL elements, including an anode region and a cathode region connected in series. The chip is connected to a sub-mount with a metallization pattern, which connects each electrically separate region on the conductive layer in series. In one aspect, the metallization pattern connects the anode region of a first electrically separate region to the cathode region of a second electrically separate region. The metallization pattern may also comprise cuts that maintain electrical separation between the anode and cathode regions on each conductive layer region, and that align with the etched regions.

A driver circuit includes a fly capacitor with a first end and a second end. The driver circuit includes a laser diode having an anode and a cathode. The driver circuit is configured to operate in first and second operating states. The anode is coupled to the first end of the fly capacitor. In the first operating state, the cathode is coupled to a first voltage supply node, the first end of the fly capacitor is coupled to a second voltage supply node, and the second end of the fly capacitor is coupled to a first reference terminal. In the second operating state, the cathode is coupled to a second reference terminal and decoupled from the first voltage supply node, the first end of the fly capacitor is decoupled from the second voltage supply node, and the second end of the fly capacitor is coupled to a third reference terminal.

A method (900) includes a gain current (I.sub.GAIN) to an anode of a gain-section diode (D.sub.0) disposed on a shared substrate of a tunable laser (310), delivering a modulation signal to an anode of an Electro-absorption section diode (D.sub.2) disposed on the shared substrate of the tunable laser, and receiving a burst mode signal (330) indicative of a burst-on state or a burst-off state. When the burst mode signal is indicative of the burst-off state, the method includes sinking a sink current (I.sub.SINK) away from the gain current at the anode of the gain-section diode. When the burst mode signal transitions to be indicative of the burst-on state from the burst-off state, the method includes ceasing the sinking of the sink current away from the gain current and delivering an overshoot current (I.sub.OVER) to the anode of the gain-section diode.

A pulsed laser diode array driver includes an inductor having a first terminal configured to receive a source voltage, a source capacitor coupled between the first terminal of the inductor and ground, a bypass capacitor connected between a second terminal of the inductor and ground, a bypass switch connected between the second terminal of the inductor and ground, a laser diode array with one or more rows of laser diodes, and one or more laser diode switches, each being connected between a respective row node of the laser diode array and ground. The laser diode switches and the bypass switch are configured to control a current flow through the inductor to produce respective high-current pulses through each row of the laser diode array, each of the high-current pulses corresponding to a peak current of a resonant waveform developed at that row of the laser diode array.

A device includes: a laminate including first and second regions adjacent to respective both sides of an isolation groove; a mesa stripe structure adjacent to the first region on the laminate and extending in the first direction; a bank structure adjacent to the second region on the laminate and extending in the first direction; and an electrode pattern. The isolation groove has an inner surface including a first wall surface adjacent to the first region, a second wall surface adjacent to the second region, and a bottom surface between the first and second regions. The ridge electrode extends from the side of the mesa stripe structure, along a second direction, toward the bank structure, and not beyond the second wall surface. The connection electrode is narrower in width in the first direction than any one of the ridge electrode and the pad electrode.