Mixers with improved linearity are disclosed. A diode or FET ring mixer is implemented with at least one parallel shunt element coupled with the ring mixer, the shunt element providing shunt to a diode or FET, for example, to reduce the effect of nonlinear or off resistance and/or capacitance. Linearity, isolation, symmetry, even order harmonics of the ring mixer, or any combination thereof can be improved as a result. The linearity of the ring mixer with parallel shunt resistors can be further improved by adding series resistors in the ring according to certain embodiments.

A switch circuit, a mixer, and an electronic device, where the switch circuit includes a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, both a gate of the first MOS transistor and a gate of the fourth MOS transistor are connected to a first port, and both a gate of the second MOS transistor and a gate of the third MOS transistor are connected to a second port; and a lead between the gate of the first MOS transistor and the first port, a lead between the gate of the second MOS transistor and the second port, a lead between the gate of the third MOS transistor and the second port, and a lead between the gate of the fourth MOS transistor and the first port all have an equal length. In this way, linearity is relatively high.

Pulse generation circuitry includes edge generation circuitry and edge combination circuitry. The edge generation circuitry includes a first digital-to-time converter (DTC) configured to input a first phase signal that includes a first phase edge and a second phase signal that includes a second phase edge. The edge generation circuitry is configured to generate a first pulse edge signal comprising a first pulse edge at a selected location between the first phase edge and the second phase edge. The edge combination circuitry is configured to combine the first pulse edge signal and a second pulse edge signal including a second pulse edge to generate a pulse signal.

A configurable passive mixer is described herein. According to one exemplary embodiment, the passive mixer comprises a clock generator, a controller, and a plurality of passive mixer cores connected in parallel. The clock generator comprises a local oscillator drive unit for each passive mixer core. The controller varies an effective transistor size of the passive mixer by separately configuring each of the passive mixer cores to enable/disable each passive mixer core. For example, the controller may selectively enable one or more of the passive mixer cores to vary the effective transistor width of the passive mixer. As the performance requirements and/or the operating communication standard change, the controller may re-configure each passive mixer core.

A user equipment (UE), receiver and method are generally described herein. The UE may include a mixer, a local oscillator (LO) and an analog-to-digital converter (ADC). The mixer may downconvert a differential radio frequency (RF) signal using LO signals and provide downconverted signals to the ADC. The mixer may provide decoupled lowpass filtering. The lowpass filter capacitors may retain charge when discharging is completed. For each differential signal, the mixer may have an input pullup resistor, first switches receiving the signal and driven by different LO signals, second switches receiving signals from the first switches such that connected pairs of switches may have driven by different LO signals, an ADC input resistor, charging capacitors each connected between first switches driven by the same LO signal, and grounding capacitors each connected to second switches associated with different RF signal outputs and driven by different LO signals.

The disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as long term evolution (LTE). An operation method of a device for upconversion in a wireless communication system is provided. The method includes receiving a first local oscillator (LO) signal, generating a second LO signal, based on the first LO signal and cross-coupled latches, receiving an input signal, generating an upconverted frequency, based on the second LO signal and the input signal, generating an output signal obtained by processing a harmonic component included in the upconverted frequency, and transmitting the generated output signal.

A discrete-time harmonic rejection mixer, an input device, and methods for using the same are described herein. In one example, a discrete-time harmonic rejection mixer includes a switched-capacitor network and a switch controller. The switched-capacitor network includes first, second, and third switched capacitor sub-circuits, each including a pair of capacitors and a set of switches. The switch controller is coupled to the switched-capacitor network, and is configured to operate the sets of switches. More specifically, the switch controller is configured to operate the sets of switches in an out of phase manner to produce the harmonic rejection effect. Capacitance values for the first pair of capacitors are roughly equal to capacitance values for the third pair of capacitors. An input device, method, and harmonic rejection circuit exhibiting the above features are provided as examples.

A clock generator has a buffer stage circuit, a passive mixer, and a channel selecting circuit. The buffer stage circuit receives a plurality of first reference clocks having a same first frequency but different phases. The passive mixer receives the first reference clocks from the buffer stage circuit, receives a plurality of second reference clocks having a same second frequency but different phases, and mixes the first reference clocks and the second reference clocks to generate a mixer output, wherein the second frequency is different from the first frequency. The channel selecting circuit extracts a plurality of third reference clocks from the mixer output, wherein the third reference clocks have a same third frequency but different phases, and the third frequency is different from the first frequency and the second frequency.

An adjustable mixer is disclosed that is capable of operating in different modes in order to satisfy the mixing requirement of multiple radio access technologies (RATs). The adjustable mixer includes a LO signal generating portion and a mixing portion. Depending on the mixing requirements of the RAT, the adjustable mixer can operate in any one of multiple modes, each mode having a specific configuration for the LO signal generating portion and the mixing portion. The LO signal generating portion generates a LO signal having a particular duty cycle, depending on the selected mode, for use by the mixing portion. The mixing portion has an adjustable circuit configuration that can be dynamically reconfigured based on the selected mode, and which allows the mixing portion to successfully mix received signals using the corresponding LO signals generated by the LO signal generating portion.

A signal mixing circuit device and a receiver are disclosed, the signal mixing circuit device comprising first to fourth mixers, first and second signal amplifying circuits, a signal strength detector, a controller and an attenuator. A signal strength value for the output from the first signal amplifying circuit is detected using the signal strength detector. If the signal strength value is less than a first threshold, a high-gain path is initiated, so that noises respectively input to the first and second mixers together with local oscillator signals are eliminated by the fourth and third mixers respectively, thereby ensuring a high signal-to-noise ratio. If the signal strength value is greater than a second threshold, a low-gain path is initiated, which partially reuses the circuit of the high-gain path, thereby effectively reducing the overall circuit area and decreasing chip cost and power consumption.