Patent classifications
H03F2200/24
HIGH-SPEED, LOW DISTORTION RECEIVER CIRCUIT
A receiver circuit has a first stage circuit having a first stage input and a first stage output, the first stage output setting a first stage common mode voltage; a second stage circuit having a second stage input connected to the first stage output, and a second stage output setting a second stage common mode voltage; and a buffer circuit having a trip point voltage, connected to the second stage output. The first stage circuit can include circuit elements configured to establish the first stage common mode voltage so that the second stage common mode voltage matches the trip point voltage. The second stage circuit can include a self-biased amplifier.
Circuits and methods to reduce distortion in an amplifier
A device to reduce distortion in an amplifier includes an input transistor configured to generate a voltage based on an input signal. The device further includes a diode connected transistor that is configured to sink the current. The diode connected transistor includes an output terminal, and a control terminal, where the output terminal is coupled to a control terminal. The device further includes a current source circuit that coupled to the control terminal. The device additionally includes an impedance element that coupled to the output terminal at a first node and to the control terminal and the current source circuit at a second node.
CIRCUITS AND METHODS TO REDUCE DISTORTION IN AN AMPLIFIER
A device to reduce distortion in an amplifier includes an input transistor configured to generate a voltage based on an input signal. The device further includes a diode connected transistor that is configured to sink the current. The diode connected transistor includes an output terminal, and a control terminal, where the output terminal is coupled to a control terminal. The device further includes a current source circuit that coupled to the control terminal. The device additionally includes an impedance element that coupled to the output terminal at a first node and to the control terminal and the current source circuit at a second node.
Method for generating a bias current for biasing a differential pair of transistors and corresponding integrated circuit
An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.
METHOD AND APPARATUS FOR SUPPLYING VOLTAGE TO AMPLIFIER USING MULTIPLE LINEAR REGULATORS
Various embodiments disclose a method and a device. The device includes: an antenna; a switching regulator; a communication chip including an amplifier, a first linear regulator operably connected to the amplifier and the switching regulator and configured to be supplied with a first voltage from the switching regulator, and a second linear regulator operably connected to the amplifier and the switching regulator and configured to be supplied with a second voltage higher than the first voltage from the switching regulator, the communication chip configured to transmit a radio-frequency signal outside of the electronic device through the antenna; and a control circuit. The control circuit is configured to produce an envelope of an input signal input to the amplifier in connection with the radio-frequency signal and to provide the produced envelope to at least one of the first linear regulator or the second linear regulator. The first linear regulator is configured to provide a third voltage corresponding to the envelope to the amplifier using the first voltage based on the envelope having a voltage in a first range. The second linear regulator is configured to provide a fourth voltage higher than the third voltage to the amplifier using the second voltage based on the voltage of the envelope being in a second range including values larger than values included in the first range.
VARIABLE GAIN AMPLIFIER WITH SUBTHRESHOLD BIASING
This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.
OPERATIONAL AMPLIFIER USING SINGLE-STAGE AMPLIFIER WITH SLEW-RATE ENHANCEMENT AND ASSOCIATED METHOD
An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal.
VARIABLE GAIN AMPLIFIER WITH SUBTHRESHOLD BIASING
This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.
AMPLIFIER
An amplifier includes an amplifier circuit 10 having a characteristic changing in accordance with a thermal history, and a bias circuit 20 that includes an element subjected to a thermal history corresponding to the thermal history of the amplifier circuit, and supplies a bias voltage to the amplifier circuit. The bias voltage changes based on a characteristic of the element that changes in accordance with the thermal history of the element.
METHOD FOR GENERATING A BIAS CURRENT FOR BIASING A DIFFERENTIAL PAIR OF TRANSISTORS AND CORRESPONDING INTEGRATED CIRCUIT
An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.