H03F2203/30036

APPARATUS AND METHOD FOR DYNAMICALLY BIASED BASEBAND CURRENT AMPLIFIER

An amplifier circuit is provided. The amplifier circuit includes an amplifier stage; a plurality of variable transistors connected to the amplifier stage; a transconductor connected to at least one of the plurality of variable transistors; and a hybrid differential envelope detector and full-wave rectifier connected to the transconductor.

Apparatus and method for dynamically biased baseband current amplifier

A dynamically biased baseband current amplifier is provided. The dynamically biased baseband current amplifier includes an input interface; a controller; a variable resistor network; an amplifier stage; a hybrid differential envelope detector and full-wave rectifier; a transconductor; a first variable transistor; a second variable transistor; a third variable transistor; and a fourth variable transistor.

Power amplifier using multi-path common-mode feedback loop

A power amplifier using multi-path common-mode feedback loops for radio frequency linearization is disclosed. In one aspect, a complementary metal oxide semiconductor (CMOS) power amplifier containing cascoded n-type field effect transistors (NFETs) and cascoded p-type FETs (PFETs) may have a common-mode feedback network and provides bias voltages that are dynamically varying with the signal power to keep the output common-mode fixed around a half-supply level, while the small-signal and large-signal transconductances of the FET's are kept balanced. A further feedback network may be associated with the supply voltage to assist in providing a symmetrical supply signal. The symmetrical supply signal allows for supply variations without introducing distortion for the power amplifier stage.

Class AB monticelli output stage design with bias temperature instability tolerance

In an example, a system includes an amplifier having an output stage configured to provide an output voltage, where the output stage includes a p-channel transistor and an n-channel transistor. The system includes a sense transistor having a gate coupled to a gate of the p-channel transistor, where the sense transistor is configured to sense a current of the p-channel transistor and produce a sense current. The system includes a current mirror coupled to the sense transistor and configured to provide the sense current to a gate of a control transistor, the control transistor having a source coupled to the gate of the p-channel transistor. The system includes a reference current source coupled to the control transistor and configured to provide a reference current. The control transistor is configured to adjust a gate current provided to the p-channel transistor based on comparing the sense current to the reference current.

POWER AMPLIFIER USING MULTI-PATH COMMON-MODE FEEDBACK LOOP
20250226802 · 2025-07-10 ·

A power amplifier using multi-path common-mode feedback loops for radio frequency linearization is disclosed. In one aspect, a complementary metal oxide semiconductor (CMOS) power amplifier containing cascoded n-type field effect transistors (NFETs) and cascoded p-type FETs (PFETs) may have a common-mode feedback network and provides bias voltages that are dynamically varying with the signal power to keep the output common-mode fixed around a half-supply level, while the small-signal and large-signal transconductances of the FETs are kept balanced. A further feedback network may be associated with the supply voltage to assist in providing a symmetrical supply signal. The symmetrical supply signal allows for supply variations without introducing distortion for the power amplifier stage.

BUFFER AND INTEGRATED CIRCUIT
20250337399 · 2025-10-30 ·

Disclosed are buffer and integrated circuit. The buffer comprises: an operational amplifier; a voltage-voltage feedback network for the op-amp, whose first end is coupled to inverting input-terminal of op-amp; an isolation-resistor, whose first end is coupled to an output-terminal of the buffer; first and second sets of switches, wherein in the case where the buffer drives first capacitive load, output-terminal of op-amp is coupled to the buffer's output-terminal via at least one switch in the first set, second end of network is coupled to the buffer's output-terminal via at least one switch in the first set, and in the case where the buffer drives second capacitive load, output-terminal of op-amp is coupled to second end of resistor via at least one switch in the second set, second end of network is coupled to output-terminal of op-amp via at least one switch in the second set.