A programmable gain amplifier includes a first gain stage having a first bias current path and a first intermediate node, a second gain stage having a second bias current path and a second intermediate node, a third gain stage having a third bias current path and a third intermediate node, a fourth gain stage having a fourth bias current path and fourth intermediate node, a first resistor coupled between the first intermediate node and the second intermediate node, and a second resistor coupled between the third intermediate node and the fourth intermediate node.

A programmable transimpedance amplifier (TIA) includes a plurality of signal paths between an output of a common emitter amplifier and the output of the TIA. The TIA is programmed by selecting one of the signal paths, because the paths have different parameters (e.g. different bandwidth). Thus, the bandwidth can be programmed by selecting the appropriate path. The common emitter amplifier's output is coupled to the inputs of common base amplifiers in each path. The inputs have low impedance. Therefore, having multiple paths does not significantly degrade the amplifier performance. High bandwidth can be provided.

According to one embodiment, an operational amplifier includes first and second input terminals, an output terminal, differential circuitry, and output circuitry. The differential circuitry including first and second nodes, and first and second transistors. The output circuitry including third through fifth nodes, and third through eighth transistors. The third transistor being coupled to the first node at a gate and coupled to the third node at one end. The fourth transistor being coupled to the second node at a gate and coupled to the fourth node at one end. The fifth transistor being coupled to the fourth node at a gate and coupled to the third node at one end. The sixth transistor being coupled to the fourth node at each of a gate and one end.

A differential crystal oscillator circuit is disclosed. The differential crystal oscillator circuit includes an output port. The output port includes a first terminal and a second terminal. A resonance port is included to couple a resonance element to the differential crystal oscillator circuit. The differential crystal oscillator includes a current source. A differential amplifier is included to excite the resonance element. The differential amplifier is coupled to the current source and the resonance port. The differential amplifier includes a plurality of transistors. The differential crystal oscillator circuit further includes a low pass filter that in combination with a transistor in the differential amplifier exhibits characteristics of a high pass filter. The differential amplifier is configured to use the current source as an active load.

Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a sampling circuit of one or more receiver arrangements that are not in autozero mode. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

The present invention provides a class AB amplifier, wherein the class AB amplifier includes a cascode stage with a filter and an output stage. The cascode stage with the filter is arranged for receiving an input signal to generate a first driving signal and a second driving signal, wherein the filter filters the input signal to generate an filtered input signal, and at least one of the first driving signal and the second driving signal is generated according to the filtered input signal. The output stage is coupled to the cascode stage, and is arranged for generating an output signal according to the first driving signal and the second driving signal.

Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from receiver arrangements that are not in autozero mode using multiplexer circuitry. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

The present invention provides a class AB amplifier, wherein the class AB amplifier includes a cascode stage with a filter and an output stage. The cascode stage with the filter is arranged for receiving an input signal to generate a first driving signal and a second driving signal, wherein the filter filters the input signal to generate an filtered input signal, and at least one of the first driving signal and the second driving signal is generated according to the filtered input signal. The output stage is coupled to the cascode stage, and is arranged for generating an output signal according to the first driving signal and the second driving signal.