A power efficient (PE) amplifier includes a cascode amplifier, a transistor amplifier, and a voltage supply. The transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The voltage supply is low voltage and supplies a current to the cascode amplifier. The PE amplifier further includes a plurality of current sources which provide a total current to the transistor amplifier. The PE amplifier has, among other things, improved power gain, improved reverse isolation, improved power dissipation, and improved peak differential swing.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

An amplifier includes a first coil coupled to at least one input node. The amplifier further includes second and third coils. A first terminal of the second coil is coupled to a source terminal of a first transistor, while a second terminal of the second coil is coupled to a source terminal of a second transistor. A third coil includes first and second terminals coupled to gate terminals of the first and second transistors, respectively. Responsive to receiving an input signal, the first coil electromagnetically conveys the signal to the second and third coils.

Disclosed is a 5G (5.sup.th generation) or pre-5G communication system for supporting a data transmission rate higher than that of a 4G (4.sup.th generation) communication system such as long-term evolution (LTE). A transmission device comprises: a first amplification unit having a common source structure, including cross coupled capacitors, and amplifying an input signal; a second amplification unit, having a common gate structure, for amplifying a signal output from the first amplification unit; and a first removal unit which is connected to output terminals of the first amplification unit and input terminals of the second amplification unit and which removes at least one portion of second harmonics. The first removal unit can offset, with respect to a fundamental frequency, at least some of parasitic capacitance generated from the output terminals of the first amplification unit and the input terminals of the second amplification unit, and can ground a signal having a secondary harmonic frequency with respect to the secondary harmonic frequency.

Low noise amplifiers (LNAs) with low noise figure are provided. In certain embodiments, an LNA includes a single-ended LNA stage including an input for receiving a single-ended input signal from an antenna and an output for providing a single-ended amplified signal, a balun for converting the single-ended amplified signal to a differential signal, and a variable gain differential amplification stage for amplifying the differential signal from the balun. Implementing the LNA in this manner provides low noise figure, high gain, flexibility in controlling gain, and less sensitivity to ground/supply impedance.

Embodiments are directed to a buffer circuit that includes a first circuit and a second circuit. The first and second circuits include sets of transistors along pairs of related signal paths, each of the transistors being driven in response to two related input signals having different but related phases. The first circuit generates a first related output signal in response to one of the pairs of related signal paths and the second circuit generates a second output signal in response to another of the pairs of related signal paths. The first and second circuits provide a linear transfer function across one of the first and one of the second sets of transistors via one of the first pair and second pair of related signal paths.

A power efficient (PE) amplifier includes a cascode amplifier, a transistor amplifier, and a voltage supply. The transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The voltage supply is low voltage and supplies a current to the cascode amplifier. The PE amplifier further includes a plurality of current sources which provide a total current to the transistor amplifier. The PE amplifier has, among other things, improved power gain, improved reverse isolation, improved power dissipation, and improved peak differential swing.

There are an amplifier circuit which includes a first current source that is connected to a power supply line to which a first electric potential is supplied, a differential input circuit that is connected between the first current source and a first node and configured to receive a differential input signal, a second current source that is connected between a power supply line to which a second electric potential is supplied and the first node, and a load circuit that is connected between a power supply line to which the first electric potential is supplied and a second node, and an inductor circuit is further connected between the first node and the second node. Thereby, the amplifier circuit achieves both lower voltage and linearity.

A programmable gain amplifier includes a first gain stage having a first bias current path and a first intermediate node, a second gain stage having a second bias current path and a second intermediate node, a third gain stage having a third bias current path and a third intermediate node, a fourth gain stage having a fourth bias current path and fourth intermediate node, a first resistor coupled between the first intermediate node and the second intermediate node, and a second resistor coupled between the third intermediate node and the fourth intermediate node.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.