An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

A memory device includes a data receiver, a latch driver, and a voltage level shifter. The data receiver works in a first voltage, receives an enable signal, a reference signal, and an input data signal, and outputs an internal data signal by the first voltage. The latch driver receives a write select signal and the internal data signal, latches the internal data signal by the first voltage, and outputs at least one latch data signal by a second voltage. The voltage level shifter receives the at least one latch data signal by the second voltage and generates at least one output data signal by the at least one latch data signal. The voltage level shifter sets a voltage value of the at least one output data signal by the first voltage. The voltage value of the first voltage is greater than the voltage value of the second voltage.

A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

An apparatus is disclosed for bidirectional amplification with phase-shifting. In example implementations, an apparatus includes a phase shifter with a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between a first plus node and a second minus node, a second transistor coupled between a first minus node and a second plus node, a third transistor coupled between the first plus node and the second minus node, and a fourth transistor coupled between the first minus node and the second plus node. The bidirectional amplifier also includes a fifth transistor coupled between the first plus node and the second plus node, a sixth transistor coupled between the first minus node and the second minus node, a seventh transistor coupled between the first plus node and the second plus node, and an eighth transistor coupled between the first minus node and the second minus node.

Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.

A driver for a transmitter includes an output stage comprising a first equalizer and a second equalizer, coupled to an output circuit of the transmitter, being operable for receiving a plurality of differential input data streams to generate an equalized differential output signals, wherein the first equalizer and the second equalizer being coupled and reconfigured to form a plurality of parallel driver segments, each driver segment having a calibration circuit, at least one of the calibration circuits been enabled to control the impedance of the output circuit, the plurality of differential input data streams are processed by the first and the second equalizer to shape the plurality of differential input data streams for compensating the channel loss.

The present invention provides a decision feedback equalizer including a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit generates a first set signal and a first reset signal according to an input signal, a second set signal and a second reset signal, and the first latch circuit generates a first digital signal according to the first set signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit generates the second set signal and the second reset signal according to the input signal, the first set signal and the first reset signal, and the second latch circuit generates a second digital signal according to the second set signal and the second reset signal.

Power consumption of a signal processing circuit is reduced. Further, power consumption of a semiconductor device including the signal processing circuit is reduced. The signal processing circuit includes a reference voltage generation circuit, a voltage divider circuit, an operational amplifier, a bias circuit for supplying bias current to the operational amplifier, and first and second holding circuits. The first holding circuit is connected between the reference voltage generation circuit and the bias circuit. The second holding circuit is connected between the voltage divider circuit and a non-inverting input terminal of the operational amplifier. Reference voltage from the reference voltage generation circuit and reference voltage from the voltage divider circuit can be held in the first and second holding circuits, respectively, so that the reference voltage generation circuit can stop operating. Thus, power consumption of the reference voltage generation circuit can be reduced.

A driver for a transmitter includes an output stage comprising a first equalizer and a second equalizer, coupled to an output circuit of the transmitter, being operable for receiving a plurality of differential input data streams to generate an equalized differential output signals, wherein the first equalizer and the second equalizer being coupled and reconfigured to form a plurality of parallel driver segments, each driver segment having a calibration circuit, at least one of the calibration circuits been enabled to control the impedance of the output circuit, the plurality of differential input data streams are processed by the first and the second equalizer to shape the plurality of differential input data streams for compensating the channel loss.