H03F2203/45592

AUDIO AMPLIFIER CIRCUITRY

The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.

Ground intermediation for inter-domain buffer stages

Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.

AMPLIFIER WITH HYSTERESIS
20190288654 · 2019-09-19 ·

An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.

Amplifier with hysteresis
10418952 · 2019-09-17 · ·

An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.

Amplifier

An amplifier that amplifies a differential signal includes first and second input terminals for receiving two input signals; first and second diodes each including an anode and a cathode, the anodes being electrically connected to the first and second input terminals; first and second bias current sources being respectively electrically connected to the cathodes of the first and second diodes; an operational amplifier connected to the cathode of the first diode and the cathode of the second diode and configured to amplify a differential signal between signals generated at the cathodes of the first and second diodes; a capacitive element being electrically connected between an input and an output of the operational amplifier; and a differential amplifier provided between the operational amplifier and the first and second input terminals and configured to amplify the two input signals. The first and second bias current sources include a current mirror circuit.

AMPLIFIER
20180316323 · 2018-11-01 · ·

An amplifier that amplifies a differential signal includes first and second input terminals for receiving two input signals; first and second diodes each including anode and cathode, the anodes being electrically connected to the first and second input terminals; first and second bias current sources being respectively electrically connected to the cathodes of the first and second diodes; an operational amplifier connected to the cathode of the first diode and the cathode of the second diode and configured to amplify a differential signal between signals generated at the cathodes of the first and second diodes; a capacitive element being electrically connected between an input and an output of the operational amplifier; and a differential amplifier provided between the operational amplifier and the first and second input terminals and configured to amplify the two input signals. The first and second bias current sources include a current mirror circuit.

Amplifier circuit and amplifier circuit IC chip

An amplifier circuit includes a converter configured to convert a predefined physical quantity to a resistance value, and the resistance value converted by the converter is converted to a voltage value and then amplified. The converter includes variable resistance sensors of piezoresistance elements. A bias unit is configured to determine a bias current of the converter, and includes bias resistances. An operation amplifier unit receives, as input signals, output signals from the bias unit and the converter, and includes feedback resistances respectively connected to input and output ends of a first operational amplifier. The first operational amplifier is a whole differential operational amplifier including a common-mode feedback circuit.

Audio amplifier circuitry

The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.

METHODS AND APPARATUS TO OPERATE A BUFFER STAGE IN AMPLIFIER CIRCUITRY
20250293651 · 2025-09-18 ·

An example apparatus includes: first buffer circuitry having an input and an output; second buffer circuitry having an input and an output; a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the output of the first buffer circuitry, the second terminal of the resistor coupled to the output of the second buffer circuitry; third buffer circuitry having an input and an output, the input of the third buffer circuitry coupled to the input of the first buffer circuitry; and switch circuitry having a first terminal and a second terminal, the first terminal of the switch circuitry coupled to the input of the second buffer circuitry, the second terminal of the switch circuitry coupled to the output of the third buffer circuitry.