A differential amplifier of a memory controller may include: an amplification stage configured to amplify input differential signals to generate intermediate differential signals; a control circuit configured to control slew rates for the intermediate differential signals; and an output circuit configured to selectively perform one or more switching operations according to the intermediate differential signals to generate output differential signals.

Exemplary multipath digital microphones described herein can comprise exemplary embodiments of automatic gain control and multipath digital audio signal digital signal processing chains, which allow low power and die size to be achieved as described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can facilitate switching between multipath digital audio signal digital signal processing chains while minimizing audible artifacts associated with either the change in the gain automatic gain control amplifiers switching between multipath digital audio signal digital signal processing chains.

A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.

A voltage converter comprising: a bootstrap circuit, comprising an output capacitor, an error amplifier, a charging control circuit and a charging circuit. The charging control circuit comprises: a detection circuit, configured to detect an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit, configured to clamp an output voltage of the error amplifier to a specific range based on the detection signal. The charging circuit is configured to generate a charging signal according the output voltage of the error amplifier to the bootstrap circuit, to charge the output capacitor.

Techniques and apparatus for reducing low frequency power supply spurs in clock signals. One example circuit generally includes a first power supply circuit configured to generate a first power supply voltage on a first power supply rail, a second power supply circuit configured to generate a second power supply voltage on a second power supply rail, a clock distribution network, and a feedback circuit coupled between the second power supply rail and at least one input of the first power supply circuit. The feedback circuit may be configured to sense the second power supply voltage, to process the sensed second power supply voltage, and to output at least one feedback signal to control the first power supply circuit based on the processed second power supply voltage. The clock distribution network may include first and second sets of clock drivers powered by the first and second power supply voltages, respectively.

A balanced differential transimpedance amplifier with a single-ended input operational over a wide variation in the dynamic range of input signals. A threshold circuit is employed to either or a combination of (1) generate a varying decision threshold to ensure a proper slicing over a wide range of input current signal levels; and (2) generate a bias current and voltage applied to an input of a transimpedance stage to cancel out a dependence of the transimpedance stage voltage input on input current signal levels.

An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.

An electronic device includes a waveform generator, a comparator, and an amplifier. The waveform generator receives a voltage from a power supply to the electronic device and outputs a voltage waveform signal. The comparator compares an input signal and the voltage waveform signal to output a first pulse-width-modulated signal. The amplifier receives the first pulse-width-modulated signal and outputs a second pulse-width-modulated signal.

A programmable (multistep) resistor attenuator architecture (such as for input to a differential amplifier) provides cancellation for harmonic distortion currents. An attenuation node is coupled: (a) to an input node through R; (b) to a virtual ground through kR and a virtual ground switch Swf with on-resistance Rswf; and (c) to a differential ground through mR and a differential ground switch Swp with on-resistance Rswp. Swp can be sized relative to Swf such that a component Ipnf of Ipn through Rswp and mR to the attenuation node, and branching into kR and Rswf, matches (phase/magnitude), a harmonic current Ifn from the virtual ground through Rswf and kR to the attenuation node. Harmonic distortion cancelation at the virtual ground can be based on matching switches Swf and Swp and the resistors R, mR, kR, reducing sensitivity to PVT variations, input frequency and amplitude. The attenuator architecture is extendable to multistage configurations.

Various embodiments of the present invention relate to a power amplification device and method, wherein the power amplification device can comprise: a power amplifier; a switch mode converter for controlling a bias of the power amplifier; a comparator for providing a switching signal to the switch mode converter according to an envelope signal; and a control unit for determining whether a switching frequency of the switch mode converter is within a specific band and applying an offset to the switching frequency so as to deviate from the specific band if the switching frequency of the switch mode converter is within the specific band. Various other embodiments can be carried out.