A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.

Provided herein are apparatus and methods for protecting radio frequency (RF) amplifiers from overdrive. In certain configurations, an RF amplification system includes a plurality of RF amplification stages including a first amplification stage and a second amplification stage subsequent to the first amplification stage in a signal path. The first amplification stage includes a first stage field-effect transistor (FET), and the second amplification stage includes a second stage FET and a gate-to-drain feedback circuit electrically connected between a gate and a drain of the second stage FET. The RF amplification system further includes an overdrive detection circuit that senses a drain current of the first stage FET to detect when an overdrive condition is present, and that decreases an impedance of the gate-to-drain feedback circuit in response to detection of the overdrive condition such that a gain of the second stage FET is reduced.

Provided herein are apparatus and methods for protecting radio frequency (RF) amplifiers from overdrive. In certain configurations, an RF amplification system includes a plurality of RF amplification stages including a first amplification stage and a second amplification stage subsequent to the first amplification stage in a signal path. The first amplification stage includes a first stage field-effect transistor (FET), and the second amplification stage includes a second stage FET and a gate-to-drain feedback circuit electrically connected between a gate and a drain of the second stage FET. The RF amplification system further includes an overdrive detection circuit that senses a drain current of the first stage FET to detect when an overdrive condition is present, and that decreases an impedance of the gate-to-drain feedback circuit in response to detection of the overdrive condition such that a gain of the second stage FET is reduced.

A method and apparatus is disclosed to couple a transmission amplifier and a reception amplifier to a shared medium. An output of the transmission amplifier is directly coupled to an input of the reception amplifier to form a common connection. The transmission amplifier and the reception amplifier may receive a first amplifier bias via the common connection. In response to the first amplifier bias, the transmission amplifier provides a first communication signal to the shared medium and the reception amplifier does not provide a second communication signal from the shared medium. Alternatively, the transmission amplifier and the reception may receive a second amplifier bias via the common connection. In response to the second amplifier bias, the reception amplifier provides the second communication signal from the shared medium and the transmission amplifier does not provide the first communication signal to the shared medium.

A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.

Provided herein are apparatus and methods for overdrive protection of radio frequency (RF) amplifiers. In certain configurations, an RF amplifier includes a plurality of amplification stages and an overdrive detection circuit. The overdrive detection circuit determines whether or not the RF amplifier is in an overdrive condition based on a current of an input amplification stage. Additionally, when the overdrive detection circuit detects an overdrive condition, the overdrive detection circuit controls an impedance of one or more feedback circuits of one or more amplification stages subsequent to the input amplification stage in a signal path of the RF amplifier to reduce the RF amplifier's gain. The overdrive protection schemes herein can be used to limit large current and voltage swing conditions manifesting within amplification transistors of the RF amplifier.

A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.

An example apparatus includes: first buffer circuitry having an input and an output; second buffer circuitry having an input and an output; a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the output of the first buffer circuitry, the second terminal of the resistor coupled to the output of the second buffer circuitry; third buffer circuitry having an input and an output, the input of the third buffer circuitry coupled to the input of the first buffer circuitry; and switch circuitry having a first terminal and a second terminal, the first terminal of the switch circuitry coupled to the input of the second buffer circuitry, the second terminal of the switch circuitry coupled to the output of the third buffer circuitry.