Patent classifications
H03G3/3063
Variable-phase amplifier circuits and devices
Variable-phase amplifier circuits and devices. In some embodiments, an amplifier can include a variable-gain stage having a plurality of switchable amplification branches, with each being capable of being activated, such that a combination of one or more activated amplification branches provides respective gain level and phase shift. The plurality of switchable amplification branches can be configured such that the phase shift provided by each combination of one or more activated amplification branches compensates for a phase shift associated with the amplifier operating with the respective gain level of the variable-gain stage.
Biasing circuits for voltage controlled or output circuits
A number of biasing circuits for amplifiers including voltage controlled amplifier is presented. Also a number of field effect transistor circuits include voltage controlled attenuators or voltage controlled processing circuits. Example circuits include modulators, lower distortion variable voltage controlled resistors, sine wave to triangle wave converters, and or servo controlled biasing circuits.
Extended feedback gain tuning in TIA based current amplifier or mixer
A transimpedance amplifier (TIA) device design is disclosed. Symmetric components include first and second resistors R.sub.i, R.sub.fb, R.sub.e, R.sub.m, R.sub.x, R.sub.c, and R.sub.l, and transistors Q1-Q4. An optional mixer or cascode adds transistors Q5-Q8. Values for resistor components R.sub.x provide extended feedback gain tuning in a TIA-based current amplifier or mixer implementations without greatly affecting the input impedance or requiring more attenuators. Example values for resistor components R.sub.x range from about 50 to about 350 ohms.
Low noise amplifier circuit having multiple gains
A low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is configured to receive an input signal and to generate a bias signal. The first output stage circuit corresponding to a first wireless communication and is configured to be biased according to the bias signal and a first control signal, in order to generate a first output signal, in which the first control signal is for setting a first gain of the first output stage circuit. The second output stage circuit corresponding to a second wireless communication and is configured to be biased according to the bias signal and a second control signal, in order to generate a second output signal, in which the second control signal is for setting a second gain of the second output stage circuit.
MULTI-INPUT AMPLIFIER WITH INDIVIDUAL BYPASS PATHS
Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths to provide variable gain for individual amplifier inputs. The variable gain for an individual input is provided using an amplification stage that is common for each input of the amplifier. A variable attenuation is provided for individual inputs through a combination of a band selection switch and an attenuation selection branch. Individual inputs can be configured to bypass the variable attenuation in a high gain mode.
PROVIDING A CONSTANT IMPEDANCE AT AN INPUT OF A SIGNAL AMPLIFIER FOR DIFFERENT GAIN MODES
Disclosed herein are methods for use in operating signal amplifiers that provide impedance adjustments for different gain modes. The impedance adjustments are configured to result in a constant real impedance for an input signal at the amplifier. Some of the disclosed methods adjust impedance using switchable inductors to compensate for changes in impedance with changing gain modes. Some of the disclosed methods adjust a device size to compensate for changes in impedance with changing gain modes. By providing impedance adjustments, the amplifiers reduce losses and improve performance by improving impedance matching over a range of gain modes.
Amplifying signals using compensating impedances to improve return loss and mismatch over gain modes
Disclosed herein are methods for amplifying a signals. The methods include receiving signals at a plurality of input nodes. The methods also include configuring a gain stage to be in a selected one of a plurality of gain settings, at least some of the gain settings resulting in different impedances presented to the signal. The methods also include adjusting the resistance presented to the signal by the gain stage for the selected gain setting, the adjusted resistance being configured to provide a targeted constant value of the impedance at the input across the plurality of gain settings. The methods also include amplifying at least a portion of the received signals. Adjusting the resistance compensates for changes to the input impedance to improve return loss and mismatch over gain modes.
Receiving circuits and methods for increasing bandwidth
A receiving circuit and method for increasing bandwidth are provided. The receiving circuit includes a linear equalizer circuit and a variable gain amplifier. The linear equalizer circuit includes a first negative impedance converter, to generate a first capacitance. The variable gain amplifier is coupled to the linear equalizer circuit. The variable gain amplifier includes a first-stage gain circuit and a feedback circuit. The first-stage gain circuit is coupled to the feedback circuit, and the feedback circuit generates a zero-point at the output end of the first-stage gain circuit.
Automatic gain control circuit of transimpedance amplifier
An automatic gain control circuit of a transimpedance amplifier includes a transimpedance amplifier TIA1, a transimpedance amplifier TIA2, an NMOS transistor Q1, an NMOS transistor Q2, an error amplifier U3, and a bias current source Ib. An input terminal and an output terminal of the transimpedance amplifier TIA1 are connected to a drain and a source of the NMOS transistor Q1, respectively. An input terminal and an output terminal of the transimpedance amplifier TIA2 are connected to a drain and a source of the NMOS transistor Q2, respectively. An output terminal of the bias current source Ib is connected to a positive input terminal of the error amplifier U3 and the drain of the MOS transistor Q2.
LOW NOISE AMPLIFIER CIRCUIT HAVING MULTIPLE GAINS
A low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is configured to receive an input signal and to generate a bias signal. The first output stage circuit corresponding to a first wireless communication and is configured to be biased according to the bias signal and a first control signal, in order to generate a first output signal, in which the first control signal is for setting a first gain of the first output stage circuit. The second output stage circuit corresponding to a second wireless communication and is configured to be biased according to the bias signal and a second control signal, in order to generate a second output signal, in which the second control signal is for setting a second gain of the second output stage circuit.