A reception circuit includes an input terminal configured to receive an input current; a voltage signal circuit being configured to convert a current signal into a voltage signal; a reference voltage circuit configured to generate a reference voltage in accordance with a first feedback current; a differential amplifier circuit configured to generate a differential signal in accordance with a voltage difference between the voltage signal and the reference voltage; and an offset control circuit configured to generate the first feedback current and a second feedback current, adjust the first feedback current when the voltage signal has an average voltage value greater than the reference voltage, and subtract the second feedback current from the input current such that the offset of the differential signal falls within the tolerance when the voltage signal has an average voltage value smaller than the reference voltage.

An apparatus comprises a transistor pair including a first metal oxide semiconductor field effect transistor (MOSFET) coupled to a second MOSFET. The first MOSFET includes a first gate terminal and a first drain terminal. The second MOSFET comprises a second gate terminal and a second drain terminal. The first gate terminal is configured to receive a first signal. The second gate terminal is configured to receive a second signal that is phase shifted with respect to the first signal. An output node is coupled to the first drain terminal and the second drain terminal and configured to output a third signal that is proportional to a power of the first signal and the second signal.

A signal adjusting circuit and a receiving end circuit using the same are provided. The signal adjusting circuit is adapted to a peak detector, and includes a first amplifier and a first feedback circuit. The first amplifier receives a first input signal, and amplifies the first input signal to output a first output signal. The first feedback circuit is connected between a first input terminal and a first output terminal of the first amplifier, and is configured to determine a first gain of the first output signal. The peak detector is connected to a first output node of the first feedback circuit, so as to receive a first detection signal and detect a peak value of the first detection signal. The peak detector has a predetermined power input range, and the first feedback circuit keeps the first detection signal within the predetermined power input range.

The present disclosure provides for process and temperature compensation in a transimpedance amplifier (TIA) using a dual replica via monitoring an output of a first TIA (transimpedance amplifier) and a second TIA; configuring a first gain level of the first TIA based on a feedback resistance and a reference current applied at an input to the first TIA; configuring a second gain level of the second TIA and a third TIA based on a control voltage; and amplifying a received electrical current to generate an output voltage using the third TIA according to the second gain level. In some embodiments, one or both of the second TIA and the third TIA include a configurable feedback impedance used in compensating for changes in the second gain level due to a temperature of the respective second or third TIA via the configurable feedback impedance of the respective second or third TIA.

A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.

A light detection and ranging (LIDAR) system includes an automatic gain control (AGC) unit to reduce the dynamic range, reducing processing power and saving circuit area and cost. The system detects a return beam of a light signal transmitted to a target, having a first dynamic range in a time domain. An analog to digital converter (ADC) generates a digital signal based on the return beam. A processor can perform time domain processing on the digital signal, convert the digital signal from the time domain to a frequency domain, and perform frequency domain processing on the digital signal in the frequency domain. The AGC unit can measure a power of the return beam, and apply variable gain in the time domain to reduce a dynamic range of the return beam to a second dynamic range lower than the first dynamic range.

A single servo control loop for amplifier gain control based on signal power change over time or system to system, having an amplifier configured to receive an input signal on an amplifier input and generate an amplified signal on an amplifier output. The differential signal generator processes the amplified signal to generate differential output signals. The single servo control loop processes the differential output signal to generates one or more gain control signals and one or more current sink control signals. A gain control system receives a gain control signal and, responsive thereto, controls a gain of one or more amplifiers. A current sink receives a current sink control signal and, responsive thereto, draws current away from the amplifier input. Changes in input power ranges generate changes in the integration level of the differential signal outputs which are detected by the control loop, and responsive thereto, the control loop dynamically adjusts the control signals.

A transimpedance amplifier circuit (1) includes an amplifier (22) that amplifies a received signal, an automatic gain control (AGC) circuit (2) that controls the amplification gain of the amplifier by a first time constant in accordance with the level of the received signal, and a first selection circuit (25) that selects the first time constant from a plurality of predetermined values. This can simultaneously implement a short time constant of an AGC function necessary to instantaneously respond to a burst signal and a long time constant of the AGC function necessary to obtain a satisfactory bit error rate (BER) characteristic in a continuous signal by an inexpensive and compact circuit arrangement.

A finger biometric sensing device may include drive circuitry for generating a drive signal and an array of finger biometric sensing pixel electrodes cooperating with the drive circuitry and generating a detected signal based upon placement of a finger adjacent the array. The detected signal may include a drive signal component and a sense signal component superimposed thereon. A gain stage may be coupled to the array and drive signal nulling circuitry may be coupled to the gain stage for reducing the drive signal component from the detected signal. The drive signal nulling circuitry may include a first digital-to-analog converter (DAC) generating an inverted scaled replica of the drive signal for the gain stage. Error compensation circuitry includes a memory storing error compensation data and a second DAC coupled in series with the first DAC compensating an error in the inverted scaled replica based upon the error compensation data.

A current mirror circuit that amplifies a reference current generated by a current source at a first magnification to supply a mirror current to a load circuit. The current mirror circuit includes a first transistor and a second transistor that share a power supply, and a drain potential mirror unit that amplifies the reference current at a second magnification to generate a first current, that amplifies a generated first current at a third magnification to generate a second current, and that supplies a predetermined potential determined based on the second current to a drain of the second transistor. The mirror current is supplied from the second transistor to the load circuit based on a potential of a gate of the first transistor determined based on the reference current.