Transconductor circuits with programmable tradeoff between bandwidth and flicker noise are disclosed. An example circuit includes an input port, an output port, a plurality of transistors, and a switch arrangement that includes a plurality of switches, configured to change coupling between the input port, the output port, and the transistors to place the transconductor circuit in a first or a second mode of operation. An input capacitance of the transconductor circuit operating in the first mode is larger than when the transconductor circuit is operating in the second mode. In the first mode, having a larger input capacitance results in a decreased flicker noise because the amount of flicker noise is inversely proportional to the input capacitance. In the second mode, having a smaller input capacitance leads to an increased flicker noise but that is acceptable for wide-bandwidth applications because wide-bandwidth signals may be less sensitive to flicker noise.

A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.

A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.

A hybrid compensation system is electrically connected between a power grid and a load. The hybrid compensation system includes an active filter, a passive filter and a control unit. The active filter generates an output current. The active filter includes a switching circuit, a DC bus capacitor and a filtering inductor. The control unit includes a voltage controller, a first reactive current detector, a harmonic current compensator, a current loop controller and a modulator. The voltage controller generates a first current given signal according to a bus voltage of the DC bus capacitor and a reference voltage. The first reactive current detector generates a second current given signal. The harmonic current compensator generates a third current given signal. The current loop controller generates a control signal. The modulator generates a driving signal according to the control signal.

A hybrid compensation system is electrically connected between a power grid and a load. The hybrid compensation system includes an active filter, a passive filter and a control unit. The active filter generates an output current. The active filter includes a switching circuit, a DC bus capacitor and a filtering inductor. The control unit includes a voltage controller, a first reactive current detector, a harmonic current compensator, a current loop controller and a modulator. The voltage controller generates a first current given signal according to a bus voltage of the DC bus capacitor and a reference voltage. The first reactive current detector generates a second current given signal. The harmonic current compensator generates a third current given signal. The current loop controller generates a control signal. The modulator generates a driving signal according to the control signal.

A front end radio frequency (RF) module including one or more first filter circuits configured to implement a front end function by filtering first signals communicated between one or more first antenna and a transceiver and one or more second filter circuits configured to implement at least a portion of an additional network function within the front end RF module by filtering second signals communicated between one or more second antennas and the transceiver.

A front end radio frequency (RF) module including one or more first filter circuits configured to implement a front end function by filtering first signals communicated between one or more first antenna and a transceiver and one or more second filter circuits configured to implement at least a portion of an additional network function within the front end RF module by filtering second signals communicated between one or more second antennas and the transceiver.

The embodiments of the present disclosure are for a signal processing circuit. The signal processing circuit includes an analog circuit. The analog circuit is used for processing an initial signal it receives. The initial signal includes a target signal and a noise signal. The analog circuit includes a first processing circuit and a second processing circuit. The first processing circuit is used to increase a ratio of the target signal to the noise signal, and output a first processed signal. The second processing circuit is used to amplify the first processed signal. A gain multiple of the second processing circuit to the first processed signal varies with a frequency of the first processed signal. The first processing circuit includes a common mode signal suppression circuit used to suppress a common mode signal in the initial signal, a lowpass filter circuit, and a high-pass filter circuit.

The embodiments of the present disclosure are for a signal processing circuit. The signal processing circuit includes an analog circuit. The analog circuit is used for processing an initial signal it receives. The initial signal includes a target signal and a noise signal. The analog circuit includes a first processing circuit and a second processing circuit. The first processing circuit is used to increase a ratio of the target signal to the noise signal, and output a first processed signal. The second processing circuit is used to amplify the first processed signal. A gain multiple of the second processing circuit to the first processed signal varies with a frequency of the first processed signal. The first processing circuit includes a common mode signal suppression circuit used to suppress a common mode signal in the initial signal, a lowpass filter circuit, and a high-pass filter circuit.

An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N−1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.