A distributed power management circuit is disclosed. Herein, a phase correction in a radio frequency (RF) signal is performed by a power management integrated circuit (PMIC), a distributed PMC, and a power amplifier circuit. The power amplifier circuit includes a phase shifter circuit configured to phase-shift the RF signal based on a phase correction signal and a power amplifier configured to amplify the phase-shifted RF signal based on a modulated voltage. The distributed PMIC is configured to generate the phase correction signal and the modulated voltage based on a modulated target voltage. The PMIC is configured to generate the modulated target voltage based on a time-variant power envelope of the RF signal. As a result, the modulated voltage and the time-variant power envelope can be better aligned in time and/or phase at the power amplifier circuit to thereby improve efficiency and linearity of the power amplifier.

A distributed power management circuit is disclosed. Herein, a phase correction in a radio frequency (RF) signal is performed by a power management integrated circuit (PMIC), a distributed PMC, and a power amplifier circuit. The power amplifier circuit includes a phase shifter circuit configured to phase-shift the RF signal based on a phase correction signal and a power amplifier configured to amplify the phase-shifted RF signal based on a modulated voltage. The distributed PMIC is configured to generate the phase correction signal and the modulated voltage based on a modulated target voltage. The PMIC is configured to generate the modulated target voltage based on a time-variant power envelope of the RF signal. As a result, the modulated voltage and the time-variant power envelope can be better aligned in time and/or phase at the power amplifier circuit to thereby improve efficiency and linearity of the power amplifier.

A power amplifier circuit supporting phase correction in a radio frequency (RF) signal is disclosed. The power amplifier circuit includes a power amplifier configured to amplify an RF signal based on a modulated voltage. The power amplifier circuit also includes a phase correction circuit configured to generate a phase correction signal based on the modulated voltage to thereby cause a phase change in the RF signal before the RF signal is amplified by the power amplifier. As a result, the modulated voltage and the time-variant power envelope can be better aligned in time and/or phase at the power amplifier circuit to thereby improve efficiency and linearity of the power amplifier circuit.

A power amplifier circuit supporting phase correction in a radio frequency (RF) signal is disclosed. The power amplifier circuit includes a power amplifier configured to amplify an RF signal based on a modulated voltage. The power amplifier circuit also includes a phase correction circuit configured to generate a phase correction signal based on the modulated voltage to thereby cause a phase change in the RF signal before the RF signal is amplified by the power amplifier. As a result, the modulated voltage and the time-variant power envelope can be better aligned in time and/or phase at the power amplifier circuit to thereby improve efficiency and linearity of the power amplifier circuit.

A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.

A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.

A superconducting quantum circuit apparatus, including: two or four Josephson parametric oscillators, JPOs, each including: a SQUID; and a pump line, with a pump signal supplied thereto, providing a magnetic flux penetrating through the loop of the SQUID, the JPOs oscillating parametrically in response to the pump signal supplied to the pump line; a coupler to couple the two or four JPOs; and a phase adjuster that varies a relative phase between or among pump signals supplied respectively to the pump lines of the two or four JPOs for parametric oscillation, to vary a strength of a two-body or four-body interaction.

A superconducting quantum circuit apparatus, including: two or four Josephson parametric oscillators, JPOs, each including: a SQUID; and a pump line, with a pump signal supplied thereto, providing a magnetic flux penetrating through the loop of the SQUID, the JPOs oscillating parametrically in response to the pump signal supplied to the pump line; a coupler to couple the two or four JPOs; and a phase adjuster that varies a relative phase between or among pump signals supplied respectively to the pump lines of the two or four JPOs for parametric oscillation, to vary a strength of a two-body or four-body interaction.

Phase shifters such as networks that can be used in MMIC (Monolithic Microwave Integrated Circuit) and hybrid digital phase shifters, for low loss, wide bandwidth, and high linearity. A digital phase shifter includes input port for receiving signals and output ports for transmitting the signals. Multiple transmission lines are arranged between the input and output ports of the phase shifter. The transmission lines are arranged in a ring with first pair of the transmission lines which are arranged in series in a first path and second pair of the transmission lines arranged in series in a second path. One of the transmission lines of the first and second pairs include quarter-wave hybrid coupled line with coupled-ports and through-ports terminated in short-circuit. Hybrid coupled line can be a Lange coupler with or without RF crossover.

Phase shifters such as networks that can be used in MMIC (Monolithic Microwave Integrated Circuit) and hybrid digital phase shifters, for low loss, wide bandwidth, and high linearity. A digital phase shifter includes input port for receiving signals and output ports for transmitting the signals. Multiple transmission lines are arranged between the input and output ports of the phase shifter. The transmission lines are arranged in a ring with first pair of the transmission lines which are arranged in series in a first path and second pair of the transmission lines arranged in series in a second path. One of the transmission lines of the first and second pairs include quarter-wave hybrid coupled line with coupled-ports and through-ports terminated in short-circuit. Hybrid coupled line can be a Lange coupler with or without RF crossover.