Patent classifications
H03H9/0085
Duplexer
A duplexer includes a reception filter that is connected between a reception terminal and an antenna terminal and includes one or a plurality of series resonators that are acoustic wave resonators, and a transmission filter that is connected between a transmission terminal and the antenna terminal and includes one or a plurality of acoustic wave resonators, a resonance frequency of a first series resonator that is one of the one or the plurality of series resonators and is closest to the antenna terminal in the reception filter being higher than an upper limit frequency of a reception band of the reception filter.
HIGH FREQUENCY FILTER WITH PHASE COMPENSATING CIRCUIT
A high-frequency filter including first and second signal terminals, a filter circuit having a passband and a stopband and being connected between the first signal terminal and the second signal terminal, and an additional circuit connected in parallel with the filter circuit between the first signal terminal and the second signal terminal. The filter circuit is configured to provide a first output signal responsive to receipt of an input signal. The additional circuit has an attenuation band within the stopband, and is configured to provide a second output signal responsive to receiving the input signal, the first and second output signals having phase components opposite to each other in the attenuation band.
Filter device having a first inductance in a chip substrate and a second inductance in a mounting substrate
A filter device with a ladder circuit configuration includes series arm resonators and parallel arm resonators, a filter component mounted on a mounting substrate and including a chip substrate and an elastic wave filter chip, a circuit configuration in which a plurality of series arm resonators and parallel arm resonators are defined by the elastic wave filter chip, and inductances are connected between ground-potential-side end portions of the plurality of parallel arm resonators and a ground potential, and in which at least one of the plurality of inductances is provided in the chip substrate and a remaining at least one inductance is provided in the mounting substrate.