A waveform generator is provided. The waveform generator includes a timer and a digital to analog converter (DAC). The timer periodically provides a trigger signal according to a fixed time period. In response to the trigger signal, the DAC is configured to convert first digital data into output voltage of an analog signal. A data hold register is configured to store second digital data that corresponds to the previous output voltage of the analog signal. A judgment circuit is configured to provide a first control signal according to the second digital data, and the first control signal indicates that the previous output voltage is within a first voltage range. A calculation circuit is configured to obtain the first digital data according to the second control signal, the second digital data, and a voltage variation that corresponds to the first voltage range and to update the second digital data.

A signal generator is configured to generate a signal with an amplitude sweep, the signal generator having circuitry comprising: a set of control components, each control component of the set being arranged to be switchably activated in parallel in the circuitry such that an amplitude of the signal has an intrinsic dependence on the number of the control components activated; a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling activation of a respective control component of the set of control components such that the control components are arranged to be activated or de-activated in a pre-determined order by shifting activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.

A waveform generator includes a system control unit and signal channels controlled by the system control unit and configured to supply driving signals for driving a respective transducer of an array of transducers. Each signal channel includes a sequential access memory having rows, where each row contains an instruction word configured to generate a respective step of a waveform to be generated. A memory output of the sequential access memory is defined by an output row at a fixed location. The waveform to be generated is defined by a block of instruction words. Each signal channel also includes an internal control unit that is configured to sequentially move the content of the sequential access memory, based on the instruction word currently at the memory output, so that sequences of instruction words are provided at the output row.

A waveform generator is provided. The waveform generator includes a timer and a digital to analog converter (DAC). The timer periodically provides a trigger signal according to a fixed time period. In response to the trigger signal, the DAC is configured to convert first digital data into output voltage of an analog signal. A data hold register is configured to store second digital data that corresponds to the previous output voltage of the analog signal. A judgment circuit is configured to provide a first control signal according to the second digital data, and the first control signal indicates that the previous output voltage is within a first voltage range. A calculation circuit is configured to obtain the first digital data according to the second control signal, the second digital data, and a voltage variation that corresponds to the first voltage range and to update the second digital data.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

The present disclosure provides systems and methods for an output architecture for an implantable pulse generator of a neurostimulation system. The output architecture includes a power supply, a plurality of outputs, a global source current regulator coupled to the power supply and operable to source current from the power supply to the plurality of outputs through a plurality of source current branches, a global sink current regulator operable to sink current from the plurality of outputs to ground through a plurality of sink current branches, a current source branch selector operable to select, for each of the plurality of outputs, an amount of current sourced from the plurality of source current branches, and a current sink branch selector operable to select, for each of the plurality of outputs, an amount of current sunk to the plurality of sink current branches.

A signal generator is configured to generate a signal with an amplitude sweep, the signal generator having circuitry comprising: a set of control components, each control component of the set being arranged to be switchably activated in parallel in the circuitry such that an amplitude of the signal has an intrinsic dependence on the number of the control components activated; a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling activation of a respective control component of the set of control components such that the control components are arranged to be activated or de-activated in a pre-determined order by shifting activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.