A spread spectrum clock generator circuit includes a phase comparator; an oscillator to output an output clock signal; a phase selector to select one of phases equally dividing one cycle of the output clock signal, and to generate a phase shift clock signal having a rising edge in the selected phase; and a phase shift controller to control the phase selector. The phase shift controller generates a variable phase shift amount; determines the phase of the rising edge so that the cycle of the phase shift clock signal has a length changed from the cycle of the output clock signal by the variable phase shift amount added with a fixed phase shift amount; and changes a setting of an SS modulation profile if the selected phase exceeds an upper limit, falls below a lower limit, or is within the upper and lower limits.

A spread spectrum clock generator circuit includes a phase comparator; an oscillator to output an output clock signal; a phase selector to select one of phases equally dividing one cycle of the output clock signal, and to generate a phase shift clock signal having a rising edge in the selected phase; and a phase shift controller to control the phase selector. The phase shift controller generates a variable phase shift amount; determines the phase of the rising edge so that the cycle of the phase shift clock signal has a length changed from the cycle of the output clock signal by the variable phase shift amount added with a fixed phase shift amount; and changes a setting of an SS modulation profile if the selected phase exceeds an upper limit, falls below a lower limit, or is within the upper and lower limits.

The present disclosure provides a device and method of generating a nonlinear waveform signal dissipating low power and operating at a high speed. The device includes: a digital preprocessing unit configured to quantize an effective input signal to generate a linear data signal and a residual signal that is a difference between the effective input signal and the linear data signal; a nonlinear digital-to-analog conversion circuit (DAC) having a nonlinear relationship between an input and an output and configured to convert the linear data signal into a first analog signal; a linear interpolation DAC configured to convert the residual signal into a second analog signal to enable a generation of a converted analog signal by an addition of the second analog signal to the first analog signal; and an output circuit configured to output the converted analog signal as a nonlinear waveform signal.

A circuit, for generating ultrahigh-precision digital pulse signals, comprises: a pulse edge control circuit used for delaying a signal on an input pin and accurately controlling positions of a rising edge and a falling edge of the pulse signal to accurately control the width of pulses and generate ultrahigh-precision pulses; a static calibration circuit used for calculating step size information representing the relationship between a work clock period of a system and a delay of delay cells in the pulse edge control circuit when the system is powered on to work, and storing the step size information, wherein the step size information is the number of delay cells through which the signal is propagated and passes within one system clock period; and a dynamic calibration circuit used for dynamically calculating step size information when a rising edge or a falling edge of each pulse in the input pin arrives.

The present disclosure provides a device and method of generating a nonlinear waveform signal dissipating low power and operating at a high speed. The device includes: a digital preprocessing unit configured to quantize an effective input signal to generate a linear data signal and a residual signal that is a difference between the effective input signal and the linear data signal; a nonlinear digital-to-analog conversion circuit (DAC) having a nonlinear relationship between an input and an output and configured to convert the linear data signal into a first analog signal; a linear interpolation DAC configured to convert the residual signal into a second analog signal to enable a generation of a converted analog signal by an addition of the second analog signal to the first analog signal; and an output circuit configured to output the converted analog signal as a nonlinear waveform signal.

A clock selector circuit includes a first input for receiving a reference clock signal having a reference frequency, a second input for receiving an offset clock signal having an offset frequency, a clock output for outputting the reference or offset clock signal, and switching circuitry. The switching circuitry includes a switching input and sign detector circuitry that outputs a sign signal indicating whether the reference clock signal is leading the offset clock signal in phase. In response to receiving a switching signal, the switching circuitry detects when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance, with the new signal leading the current signal if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal if not. In response, the switching circuitry switches to outputting the new clock signal.

A method for synchronized injection of impedance into high voltage (HV) transmission line is disclosed. The method includes generating, by a plurality of impedance injection units (IIUs) coupled to the HV transmission line, impedance injection waves that cumulatively form a pseudo-sinusoidal wave. The method further includes optimizing, by the plurality of IIUs, the pseudo-sinusoidal wave to represent a pure sinusoidal wave. The method further includes injecting, by the plurality of IIUs, the pseudo-sinusoidal wave, as impedance, into the HV transmission line. The plurality of IIUs form multiple connection configurations in sequence, each connection configuration comprising one IIU or multiple IIUs in series, parallel or combination thereof, coupled to the HV transmission line.

A method for synchronized injection of impedance into high voltage (HV) transmission line is disclosed. The method includes generating, by a plurality of impedance injection units (IIUs) coupled to the HV transmission line, impedance injection waves that cumulatively form a pseudo-sinusoidal wave. The method further includes optimizing, by the plurality of IIUs, the pseudo-sinusoidal wave to represent a pure sinusoidal wave. The method further includes injecting, by the plurality of IIUs, the pseudo-sinusoidal wave, as impedance, into the HV transmission line. The plurality of IIUs form multiple connection configurations in sequence, each connection configuration comprising one IIU or multiple IIUs in series, parallel or combination thereof, coupled to the HV transmission line.

A method for synchronized injection of impedance into high voltage (HV) transmission line is disclosed. The method includes generating, by a plurality of impedance injection units (IIUs) coupled to the HV transmission line, impedance injection waves that cumulatively form a pseudo-sinusoidal wave. The method further includes optimizing, by the plurality of IIUs, the pseudo-sinusoidal wave to represent a pure sinusoidal wave. The method further includes injecting, by the plurality of IIUs, the pseudo-sinusoidal wave, as impedance, into the HV transmission line. The plurality of IIUs form multiple connection configurations in sequence, each connection configuration comprising one IIU or multiple IIUs in series, parallel or combination thereof, coupled to the HV transmission line.

A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.