Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.

A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor w.sub.i,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor w.sub.i,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.

Networks, methods, and circuitries are provided that propagate an actuator signal to a plurality of devices in a respective plurality of voltage domains. The network includes a first signal path disposed between an actuator signal source and a first device. The first signal path includes a first point at which the actuator signal is in a first voltage domain. A second signal path is disposed between the actuator signal source and a second device. The second signal path includes a second point at which the actuator signal is in a second voltage domain. The first voltage domain is different from, and has a fixed relationship to, the second voltage domain. A multi-domain coupling circuitry is connected to the first point and the second point. The multi-domain coupling circuitry is configured to maintain the fixed relationship between the actuator signal at the first point and the second point.

A system (for generating multi-gated power-on control signals) includes: a multi-gated input/out (I/O) interface configured to receive at least first and second gating signals; and a gated power-on control (POC) signals generator configured to generate at least the first and second gating signals for the multi-gated I/O interface, a waveform of the first gating signal being different from a waveform of the second gating signal.

An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.

A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.

A flip-flop is provided. The flip-flop includes: a first inverter including an input terminal to receive data signal and an output terminal coupled to an input terminal of the master latch, a second inverter, a master latch including an output terminal coupled to an input terminal of a slave latch, and the slave latch including an output terminal coupled to an input terminal of the second inverter. An output terminal of the second inverter is configured as an output terminal of the flip-flop. A duration of the first clock signal inputted to the master latch is greater than a duration of the first clock signal inputted to the slave latch. A duration of the second clock signal inputted to the master latch is greater than a duration of the second clock signal inputted to the slave latch.

Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.

An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.

A passable latch circuit and variable delay chains built with one or more passable latch circuits are disclosed. The passable latch circuit has a dynamic latch including a first P-transistor, a first N-transistor, a second P-transistor, a second N-transistor and a clock input circuitry. The passable latch circuit further includes a control switch connected between the gates of the second P-transistor and the second N-transistor. The control switch has an on state and an off state, and the passable latch circuit is configured to have different delays by controlling the state of the control switch.