A method for processing a signal formed of a sequence of pulses, including at least one repetitive pattern formed of at least one pulse, the pattern being repeated in the signal with a pattern repetition period, the method including estimating the pattern repetition period of the signal and calculating, as a function of (i) an arrival date of each pulse with respect to a chosen reference arrival date, and (ii) the estimated pattern repetition period, a sequence of phases; thereafter, the method includes estimating, on the basis of the calculated sequence of phases, at least one phase value and an associated standard deviation, the phase value being associated with a phase moment representative of the repetitive pattern, and obtaining and utilizing parameters characterizing the digital signal by using the estimated phase values.

A method for processing a signal formed of a sequence of pulses, including at least one repetitive pattern formed of at least one pulse, the pattern being repeated in the signal with a pattern repetition period, the method including estimating the pattern repetition period of the signal and calculating, as a function of (i) an arrival date of each pulse with respect to a chosen reference arrival date, and (ii) the estimated pattern repetition period, a sequence of phases; thereafter, the method includes estimating, on the basis of the calculated sequence of phases, at least one phase value and an associated standard deviation, the phase value being associated with a phase moment representative of the repetitive pattern, and obtaining and utilizing parameters characterizing the digital signal by using the estimated phase values.

A memory device includes a memory array and a frequency-to-voltage converter. The memory array includes a plurality of memory cells arranged in rows and columns, and gates of the memory cells in the same row are coupled to each other and connected to a word line. The frequency-to-voltage converter coupled between the word line and a clock signal source outside the memory device receives a clock signal, and correspondingly outputs different voltages to the word line in accordance with the frequency of the clock signal.

Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

A pulse position modulation circuit includes a delay locked loop circuit configured to include a plurality of delay circuits coupled in a cascade, each of the plurality of delay circuits being configured to delay an input signal by a time width corresponding to a control signal so as to generate an output signal, a plurality of pulse generation circuits, each of which is configured to generate a pulse with a pulse width corresponding to a phase difference between a first signal and a second signal which have different phases from each other at different timings corresponding to states of the first signal and the second signal, each of the first signal and the second signal being the input signal or the output signal of the plurality of delay circuits, and a selection circuit configured to select pulses generated by the plurality of pulse generation circuits.

An electronic assembly including a plurality of electrically conductive elements separated by insulative material and a digital FM demodulator circuit coupled to some of the electrically conductive elements. The FM demodulator circuit having an FM detector circuit and a DC drift reducing circuit. The FM detector circuit has a detector input and a detector output that is the output of a comparator that is AC coupled to the rest of the FM detector circuit, the detector input receiving an input signal. The DC drift reducing circuit is electrically coupled to the detector output of the comparator, the DC drift reducing circuit detecting a DC drift of the detector output, the DC drift reducing circuit being additionally coupled to an input of the comparator, the DC drift reducing circuit substantially eliminating DC drift at the output of the FM demodulator circuit.

An electronic assembly including a plurality of electrically conductive elements separated by insulative material and a digital FM demodulator circuit coupled to some of the electrically conductive elements. The FM demodulator circuit having an FM detector circuit and a DC drift reducing circuit. The FM detector circuit has a detector input and a detector output that is the output of a comparator that is AC coupled to the rest of the FM detector circuit, the detector input receiving an input signal. The DC drift reducing circuit is electrically coupled to the detector output of the comparator, the DC drift reducing circuit detecting a DC drift of the detector output, the DC drift reducing circuit being additionally coupled to an input of the comparator, the DC drift reducing circuit substantially eliminating DC drift at the output of the FM demodulator circuit.

An apparatus for monitoring radio frequency (RF) signals is disclosed. The apparatus includes an RF splitter, a set of track-and-hold circuits, a set of analog-to-digital circuits (ADC) and a frequency tracking module. The RF splitter splits a set of incoming RF signals into multiple RF signal paths. Each of the track-and-hold circuits, which is clocked at a different frequency than others, samples the incoming RF signals from a respective one of the RF signal paths. Each of the ADCs receives the sampled data from a respective one of the track-and-hold circuits. Each of the ADCs is also clocked at same frequency as a corresponding one of the track-and-hold circuits. The frequency tracking module determines a frequency of the incoming RF signals.

A method for processing a signal formed of a sequence of pulses, including at least one repetitive pattern formed of at least one pulse, the pattern being repeated in the signal with a pattern repetition period, the method including estimating the pattern repetition period of the signal and calculating, as a function of (i) an arrival date of each pulse with respect to a chosen reference arrival date, and (ii) the estimated pattern repetition period, a sequence of phases; thereafter, the method includes estimating, on the basis of the calculated sequence of phases, at least one phase value and an associated standard deviation, the phase value being associated with a phase moment representative of the repetitive pattern, and obtaining and utilizing parameters characterizing the digital signal by using the estimated phase values.