The disclosure relates to a method performed by an apparatus for decoding an encoded signal in a communication system according to an embodiment of the disclosure may include an operation of receiving an encoded signal including a plurality of codeword bits, an operation of determining a first log-likelihood ratio (LLR) for the plurality of codeword bits, and an operation of performing iterative decoding a predetermined number of times based the first LLR, and the plurality of codeword bits may include a codeword bit included in a first subset and a codeword bit included in a second subset, and the operation of performing iterative decoding may include determining a second LLR only for the codeword bit included in the first subset of the plurality of codeword bits, and estimating, based on the second LLR, a bit value only for the codeword bit included in the first subset.

A method, an apparatus and a system for determining stress on a low density parity check (LDPC) process for a network using orthogonal frequency division multiplexing (OFDM).

Provided are a decoding system including a receiving device and a transmitting device. The receiving device comprises a demapper configured to convert received data into a log likelihood ratio (LLR) signal and output the LLR signal, a deparser configured to rearrange the LLR signal by deparsing the LLR signal into orthogonal frequency division multiplex (OFDM) symbols, a codeword loader configured to output the rearranged LLR signal in units of codewords, a decoder controller configured to control a maximum iteration number and the number of decoders to be enabled according to a state of the received data and a low-density parity check (LDPC) decoder configured to repeatedly decode the LLR signal in units of codewords, according to the controlled number of decoders, as many times as the controlled maximum iteration number, wherein the received data comprises real data and a packet extension corresponding to a pre-FEC (forward error correction) padding factor.

A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.

Disclosed is a network-based hyperdimensional system having an encoder configured to receive input data and encode the input data using hyperdimensional computing to generate a hypervector having encoded data bits that represent the input data. The network-based hyperdimensional system further includes a decoder configured to receive the encoded data bits, decode the encoded data bits, and reconstruct the input data from the decoded data bits. In some embodiments, the encoder is configured for direct hyperdimensional learning on transmitted data with no need for data decoding by the decoder.

This application discloses example decoding methods, example decoder, and example decoding apparatuses. One example decodine method includes performing soft decision decoding on a first sub-codeword in a plurality of sub-codewords to obtain a hard decision result. It is determined whether to skip a decoding iteration. In response to determining not to skip the decoding iteration, a first turn-off identifier corresponding to the first sub-codeword is set to a first value based on the hard decision result. The first turn-off identifier indicates whether to perform soft decision decoding on the first sub-codeword in a next decoding iteration. The soft decision decoding is not performed on the first sub-codeword in the next decoding iteration when a value indicated by the first turn-off identifier is the first value. The hard decision result is stored.

A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.

Systems and methods for implementing data protection techniques with symbol-based variable node updates for binary low-density parity-check (LDPC) codes are described. A semiconductor memory (e.g., a NAND flash memory) may read a set of data from a set of memory cells, determine a set of data state probabilities for the set of data based on sensed threshold voltages for the set of memory cells, generate a valid codeword for the set of data using an iterative LDPC decoding with symbol-based variable node updates and the set of data state probabilities, and store the valid codeword within the semiconductor memory or transfer the valid codeword from the semiconductor memory. The iterative LDPC decoding may utilize a message passing algorithm in which outgoing messages from a plurality of multi-variable nodes are generated using incoming messages (e.g., log-likelihood ratios or L-values) from a plurality of check nodes.

Low-density parity-check (LDPC) encoded data with one or more errors is received. Information associated with an early convergence checkpoint that occurs at a fractional iteration count that is strictly greater than 0 and strictly less than 1 is received. The information associated with the early convergence checkpoint is used to perform LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword, wherein the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. At the early convergence checkpoint that occurs at the fractional iteration count, it is determined whether the LDPC decoding is successful and in the event it is determined that the LDPC decoding is successful, the decoded codeword is output.

Methods, systems, and apparatuses for stall mitigation in iterative decoders are described. A codeword is received from a memory device. The codeword is iteratively error corrected based on a first bit flipping criterion. A stall condition in the multiple error correction iterations is detected. In response to the detection, the codeword is error corrected based on a second bit flipping criterion that is different from the first bit flipping criterion.