A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.

Examples described herein utilize multi-layer neural networks to decode encoded data (e.g., data encoded using one or more encoding techniques). The neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing the neural network decoders. In this manner, neural networks described herein may be used to implement error code correction (ECC) decoders.

Disclosed are a storage node and method. The storage node includes a storage device, and a smart NIC, where the smart NIC is configured to receive a write request including original data to be stored in the DFS, and responsive to the receiving, generate parity data by performing erasure coding on the original data, and store the parity data and the original data directly from the smart NIC to the storage device, and receive, from a client device or another client device, a read request for data stored in the DFS, where the smart NIC is further configured to, responsive to receiving the read request, fetch a portion of the original data and the parity data directly from the storage device, and recover another portion of the original data by applying forward error correction (FEC) decoding to the fetched portion of the original data using the fetched parity data.

Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Methods and apparatus associated with storing data in high or low energy zones are described. Example apparatus include a data storage system (DSS) that protects a message using an erasure code (EC). A location in the DSS may have an energy efficiency rating or a latency. Example apparatus include circuits that produce EC encoded data that has a likelihood of use, that select a location to store the EC encoded data in the DSS based on the energy efficiency rating, the latency, or the likelihood of use, that store the EC encoded data in the location, and that compute an order of retrieval for EC encoded data stored in the location. The order of retrieval may be based on the energy efficiency rating or the latency. The EC encoded data may also have a priority based on the number of erasures for which the EC corrects.

Provided are a data checking method and device. The method includes: receiving a transmission signal containing a first data block and transmitted by a transmission node, wherein the length of the first data block is N bits, the first data block is generated by performing an FEC encoding on a second data block which has a length of K bits, and the second data block is generated by performing a CRC encoding on a third data block which has a length of L bits, where N, K and L are all positive integers, and N≧K>L; obtaining a first estimation data block of the first data block according to the transmission signal, and obtaining a second estimation data block of the second data block according to the transmission signal; and checking the third data block according to a relationship between the first estimation data block and an FEC code space and/or a CRC check result of the second estimation data block. By means of the technical solution provided in the present disclosure, the problems that a transmission rate decreases due to the fact that a CRC check code is too long and a false detection rate cannot be ensured due to the fact that the CRC check code is too short are solved.

A Bluetooth data packet processing method is disclosed. According to the Bluetooth data packet processing method, a standard Bluetooth baseband protocol is extended, so that a Bluetooth node can also support polar encoding/decoding based on compatibility with the standard Bluetooth protocol. When processing a Bluetooth data packet, the Bluetooth node may choose to perform polar encoding on the data packet by using an extended Bluetooth baseband protocol, to improve demodulation performance of a Bluetooth receiver, and improve an anti-interference capability of a Bluetooth system.

A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.