H03M5/02

Quaternary decoder
09742431 · 2017-08-22 · ·

Embodiments are provided for a quaternary decoder that includes a plurality of decoder circuits, each decoder circuit coupled to a respective input line of a plurality of quaternary interface lines and to a respective pair of binary output lines; and a control logic circuit having a plurality of control signal lines coupled to each of the plurality of decoder circuits, the control logic circuit configured to: output a first sequence of logic levels, and output a second sequence of logic levels after the first sequence is complete; wherein at a time after the second sequence is complete, each decoder circuit is configured to output a pair of binary data values that correspond to a quaternary state of the respective input line, the quaternary state being one of four quaternary states including a logic high state, a logic low state, a floating state, and a tie-back state.

Electronic device, method, and system for converting digital audio signal received in wired or wireless manner into analog audio signal

According to an embodiment of the disclosure, disclosed is an electronic device that includes a first connector electrically connectable to an external electronic device, a second connector electrically connectable to an external audio plug, a wireless communication circuit, and at least one processor. When the electronic device is connected to the external electronic device through the first connector, the at least one processor may receive a first digital audio signal from the external electronic device through the first connector, convert the received first digital audio signal into a first analog audio signal, and output the converted first analog audio signal through the second connector. When the electronic device is connected to the external electronic device through the wireless communication circuit, the at least one processor may receive a second digital audio signal from the external electronic device through the wireless communication circuit, convert the received second digital audio signal into a second analog audio signal having a sound quality lower than that of the first analog audio signal, and output the converted second analog audio signal through the second connector.

ETHERNET-BASED VEHICLE CONTROL SYSTEM AND METHOD
20220144211 · 2022-05-12 · ·

Disclosed are Ethernet-based vehicle control system and method. The system includes: a router for connecting a vehicle internal network and a vehicle external network when the vehicle internal network is formed by connecting an engine and a vehicle electronic element including a controller and a sensor; and a remote start module for performing remote start based on a remote start signal transmitted from a remote controller through the vehicle external network, wherein whether or not to perform the remote start is determined based on drive system state information generated by the vehicle electronic element and transferred via the router. When performing a remote start is controlled in response to an engine RPM during the remote start, efficient management of engine protection and fuel consumption can be achieved. When performing a remote start is controlled in response to the position of the transmission, safe remote start can be achieved.

Memory device, method of calibrating signal level thereof, and memory system having the same

A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.

COMMUNICATIONS METHOD AND APPARATUS
20230291615 · 2023-09-14 ·

Communications method and apparatus include encoding information into a high-peakedness designed pulse train, converting the designed pulse train into a low-peakedness signal suitable for modulating a narrowband carrier to generate a physical communication signal with desired spectral and temporal properties, and generating and transmitting the physical communication signal. The communications method and apparatus also include receiving and demodulating the physical communication signal, and further converting the demodulated signal into a high-peakedness received pulse train corresponding to the designed pulse train, so that the encoded information may be extracted from the received pulse train.

Circuits for converting SFQ-based RZ and NRZ signaling to bilevel voltage NRZ signaling

Edge-sensitive, state-based single flux quantum (SFQ) based circuitry and related methods convert return-to-zero (RZ) or non-return-to-zero (NRZ) encoded SFQ-pulse-based signals to bilevel NRZ phase signals that can subsequently be converted to bilevel voltage signals by an output amplifier (OA). The SFQ-based circuitry can be integrated with a current amplification stage of a driver that can be coupled to a stage of the OA. The SFQ-based circuitry can be made to be compatible with RQL-encoded input signals that can be either RZ or NRZ. The SFQ-based circuitry can thus be compatible with both wave-pipelined (WPL) and phase-mode (PML) RQL circuitry. Because the SFQ-based circuitry and related methods are edge-sensitive and state-based, they can function at system clock rates in excess of 1 GHz with reduced glitches and improved bit error rates as compared to other superconducting RZ-NRZ conversion circuitry and methods.

SERIAL BUS PROTOCOL
20230195679 · 2023-06-22 ·

In accordance with an embodiment, a system includes: a primary device configured to be connected to at least one secondary device via serial bus having a data wire and a clock wire. The primary device is configured to: provide a clock signal on the clock wire; and transmit a frame comprising control bits on the serial bus, wherein a number of control bits transmitted on the serial bus at at least one location of the frame indicates a format of the frame.

Fluid measurement interface systems and methods

A fluid measurement system includes a signal processor and a processing system. The signal processor is configured and adapted to produce a serial word that is indicative of a fluid characteristic that is configured to be communicated externally of the signal processor. The processing system is operatively connected to the signal processor to read the serial word and decode the serial word. A method for transmitting a fluid characteristic between a sensor system and a processing system includes producing a serial word that is indicative of a fluid characteristic value with a signal processor. The method includes transmitting the serial word externally of the signal processor. The method includes reading and decoding the serial word with a processing system to determine the fluid characteristic value.

Fluid measurement interface systems and methods

A fluid measurement system includes a signal processor and a processing system. The signal processor is configured and adapted to produce a serial word that is indicative of a fluid characteristic that is configured to be communicated externally of the signal processor. The processing system is operatively connected to the signal processor to read the serial word and decode the serial word. A method for transmitting a fluid characteristic between a sensor system and a processing system includes producing a serial word that is indicative of a fluid characteristic value with a signal processor. The method includes transmitting the serial word externally of the signal processor. The method includes reading and decoding the serial word with a processing system to determine the fluid characteristic value.

MEMORY DEVICE, METHOD OF CALIBRATING SIGNAL LEVEL THEREOF, AND MEMORY SYSTEM HAVING THE SAME

A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling.