Data compression/decompression methods and data compressor/de-compressor are provided. The data compression method includes the steps of scaling an input signal to generate a scaled signal; transmitting the scaled signal to a differentiator and an assembler; differentiating the scaled signal and a prior signal to generate a differentiation signal detecting zero bits of the differentiation signal to generate a zero range control signal and a zero range control word; refining the differentiation signal according to the zero range control signal to generate a refined signal; and determining to combine the zero range control word with the scaled signal or combine the zero range control word with the refined signal according to the zero range control word to generate a compressed signal.

Methods are provided for efficiently encoding and decoding multivariate correlated data sequences for transmission over multiple channels of a network. The methods include transforming data vectors from correlated sources into vectors that comprise substantially independent and correlated components, and generating a common information vector based on the correlated components, and two private information vectors. The methods also include computing the amount of information, such as Wyner's lossy common information, in the common information vector, computing rates that lie on the Gray-Wyner rate region, and choosing compression rates based on the amount of common information. The methods may be applicable, in general, to a wide range of communications and/or storage systems and, particularly, to sensor networks and multi-user virtual environments for gaming and other applications.

A stream decompression circuit is disclosed. The stream decompression circuit includes a coding length first-in-first-out (FIFO) and a calculation circuit. The coding length FIFO is coupled to a variable length coding (VLC) circuit and used to store a coding length that the VLC circuit codes sub-streams and output a specific number of bits when the coding length accumulates over the specific number of bits. The calculation circuit is coupled between the coding length FIFO and a multiplexer circuit and used to calculate a number of bits required for decompression and output an output multiplex control signal to the multiplexer circuit to control the multiplexer circuit to output the sub-streams according to a specific order.

A system collects statistical data for a data page, divides the data page into parts, analyzes the data page and the statistical data, based on compression efficiency of one or more compression methods for each part of each page, to determine a compression method for each part of page, and compresses, based on the analyzing, the parts of the data page.

According to one embodiment, a compression device includes a coding information generation unit. The unit determines code lengths that are respectively associated with a plurality of symbols, based on a frequency of occurrence of each of the plurality of symbols. When the plurality of symbols include one or more first symbols that are respectively associated with one or more first code lengths exceeding an upper limit, the unit changes the first code lengths to the upper limit, selects, from one or more second symbols of the plurality of symbols that are respectively associated with one or more second code lengths shorter than the upper limit, at least one symbol in descending associated code length order, changes at least one code length associated with the symbol to the upper limit.

Innovations in range asymmetric number system (“RANS”) coding and decoding are described herein. Some of the innovations relate to hardware implementations of RANS decoding that organize operations in two phases, which can improve the computational efficiency of RANS decoding. Other innovations relate to adapting RANS encoding/decoding for different distributions or patterns of values for symbols. For example, RANS encoding/decoding can adapt by switching a default symbol width (the number of bits per symbol), adjusting symbol width on a fragment-by-fragment basis for different fragments of symbols, switching between different static probability models on a fragment-by-fragment basis for different fragments of symbols, and/or selectively flushing (or retaining) the state of a RANS decoder on a fragment-by-fragment basis for different fragments of symbols. In many cases, such innovations can improve compression efficiency while also providing computationally efficient performance.

Systems, apparatuses, and methods related to bit string compression are described. A method for bit string compression can include determining that a particular operation is to be performed using a bit string formatted according to a universal number format or a posit format to alter a bit width associated with the bit string from a first bit width to a second bit width and performing a compression operation on a bit string formatted according to a universal number format or a posit format to alter a bit width associated with the bit string from a first bit width to a second bit width. The method can further include writing the bit string having the second bit width to a first register, performing an arithmetic operation or a logical operation, or both using the bit string having the second bit string width, and monitoring a quantity of bits of a result of the operation.

A system collects statistical data for a data page, divides the data page into parts, analyzes the data page and the statistical data, based on compression efficiency of one or more compression methods for each part of each page, to determine a compression method for each part of page, and compresses, based on the analyzing, the parts of the data page.

Embodiments of the present disclosure include techniques for compressing data using a tree encoded bit mask that may result in higher compression ratios. In one embodiment, an input vector having a plurality of values is received by a first plurality of switch circuits. Selection of the input values is controlled by sets of bits from the bit mask. The sets of bits specify locations of portions of the input vector where particular value of interest reside. The switch circuits output multiple values of the input vector, which include the particular value of interest. A second stage of switch circuits is controlled by logic circuit that detects values on the outputs of the first stage of switch circuits and outputs the values of interest. In some embodiments, the values of interest may be non-zero values of a sparse input vector, and the switch circuits may be multiplexers.

A system collects statistical data for a data page, divides the data page into parts, analyzes the data page and the statistical data, based on compression efficiency of one or more compression methods for each part of each page, to determine a compression method for each part of page, and compresses, based on the analyzing, the parts of the data page.