Patent classifications
H04B17/11
PRECISE INDOOR LOCALIZATION AND TRACKING OF ELECTRONIC DEVICES
Methods and devices useful in performing precise indoor localization and tracking are provided. By way of example, a method includes locating and tracking, via a first wireless electronic device, a plurality of other wireless electronic devices within an indoor environment. Location ambiguity mitigation is performed using characteristics of signals received by a reference node used to generate a radio frequency map of electronic devices.
PRECISE INDOOR LOCALIZATION AND TRACKING OF ELECTRONIC DEVICES
Methods and devices useful in performing precise indoor localization and tracking are provided. By way of example, a method includes locating and tracking, via a first wireless electronic device, a plurality of other wireless electronic devices within an indoor environment. Location ambiguity mitigation is performed using characteristics of signals received by a reference node used to generate a radio frequency map of electronic devices.
Transmitter device and calibration method
A transmitter device includes a transmitter circuit, a voltage generator circuit, and a calibration circuit. The transmitter circuit is configured to selectively operate in a calibration mode or a normal mode in response to a first control signal, in which the transmitter circuit has a first output terminal and a second output terminal. The voltage generator circuit is configured to generate a bias voltage, in which the bias voltage has a first level in the calibration mode and has a second level in the normal mode, and the first level is different from the second level. The calibration circuit is configured to be turned on in the calibration mode according to the bias voltage and a second control signal, in order to calibrate a level of the first output terminal and a level of the second output terminal.
Transmitter device and calibration method
A transmitter device includes a transmitter circuit, a voltage generator circuit, and a calibration circuit. The transmitter circuit is configured to selectively operate in a calibration mode or a normal mode in response to a first control signal, in which the transmitter circuit has a first output terminal and a second output terminal. The voltage generator circuit is configured to generate a bias voltage, in which the bias voltage has a first level in the calibration mode and has a second level in the normal mode, and the first level is different from the second level. The calibration circuit is configured to be turned on in the calibration mode according to the bias voltage and a second control signal, in order to calibrate a level of the first output terminal and a level of the second output terminal.
Transmitter image calibration using phase shift estimation
Techniques are presented to improve the accuracy of and reduce the time required for calibration of an in-phase/quadrature (I/Q) transmission circuit. A measurement receiver measures the I/Q mismatch, where an RF phase shift is introduced to distinguish between the transmitter and measurement receiver I/Q mismatches. Rather than assuming an amount of introduced phase shift, a measurement is used to estimate the phase shift. This phase estimate is then used to determine and correct the I/Q mismatch in the transmitter and measurement receiver. An iterative process can be used to improve the I/Q correction factors. Using simple signal processing to measure the phase shift during calibration and to perform the image calibration calculations, the phase shifter requirements can be significantly relaxed, resulting in faster design time and reduced design area/cost. This approach results in reduced calibration time, thus contributing to reduced factory production time and enabling faster live mode image calibration.
Self-contained in-phase and quadrature (IQ) image rejection calibration on heterodyne transceivers in millimeter-wave phase array system
A millimeter-wave phase array system may include massive heterodyne transceivers as its building elements. A transceiver of each element may include an IQ image rejection heterodyne transmitter and a receiver. Each transmitter may include a single DAC, a Tx I channel, and a Tx Q channel. Each receiver may include an Rx I channel, an Rx Q channel, and a single ADC. For Tx IQ image rejection calibration, amplitude and phase offsets are determined, using both the Tx I and Tx Q channels from a first element and using only one of the Rx I or Rx Q channel from a second element. The IQ channel imbalances are compensated using the offsets in analog domain. A similar procedure is used for Rx IQ image rejection calibration with alternated signal path enabling. A frequency response variation of an RF front end is detected with a single path Tx/Rx channel setup.
Self-contained in-phase and quadrature (IQ) image rejection calibration on heterodyne transceivers in millimeter-wave phase array system
A millimeter-wave phase array system may include massive heterodyne transceivers as its building elements. A transceiver of each element may include an IQ image rejection heterodyne transmitter and a receiver. Each transmitter may include a single DAC, a Tx I channel, and a Tx Q channel. Each receiver may include an Rx I channel, an Rx Q channel, and a single ADC. For Tx IQ image rejection calibration, amplitude and phase offsets are determined, using both the Tx I and Tx Q channels from a first element and using only one of the Rx I or Rx Q channel from a second element. The IQ channel imbalances are compensated using the offsets in analog domain. A similar procedure is used for Rx IQ image rejection calibration with alternated signal path enabling. A frequency response variation of an RF front end is detected with a single path Tx/Rx channel setup.
Array wall slot antenna for phased array calibration
Technologies directed to a slot antenna as a calibration antenna for a phased array antenna are described. The antenna structure includes a ground plane, a first antenna element, and a second antenna element. The first antenna element and the second antenna element are located in a first plane that is separated from the ground plane by a first distance. The second antenna element is separated from the first antenna element by a second distance. Conductive material is located in the first plane the first antenna element and the second antenna element. A portion of the conductive material adjacent to the first antenna element includes a slot antenna. A radio frequency feed point is located at the slot antenna. The conductive material electrically isolates the first antenna element and the second antenna element and radiates electromagnetic energy as a slot antenna.
Array wall slot antenna for phased array calibration
Technologies directed to a slot antenna as a calibration antenna for a phased array antenna are described. The antenna structure includes a ground plane, a first antenna element, and a second antenna element. The first antenna element and the second antenna element are located in a first plane that is separated from the ground plane by a first distance. The second antenna element is separated from the first antenna element by a second distance. Conductive material is located in the first plane the first antenna element and the second antenna element. A portion of the conductive material adjacent to the first antenna element includes a slot antenna. A radio frequency feed point is located at the slot antenna. The conductive material electrically isolates the first antenna element and the second antenna element and radiates electromagnetic energy as a slot antenna.
Mismatch detection using replica circuit
An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.