Disclosed is a transmitter that includes a demodulation circuit and a transmitting-side back-end processing circuit. When a TLV packet superimposed on a broadcast wave and transmitted with a variable data length is to be converted to split TLV packets with a fixed data length, the demodulation circuit sets a speed for switching between L and H levels of a clock signal in such a manner that the speed for first data including a packet header to be embedded in a header section of the split TLV packets is twice the speed for data subsequent to the first data. The transmitting-side back-end processing circuit QAM-modulates a signal demodulated by the demodulation circuit for cable broadcasting purposes.

Disclosed is a transmitter that includes a demodulation circuit and a transmitting-side back-end processing circuit. When a TLV packet superimposed on a broadcast wave and transmitted with a variable data length is to be converted to split TLV packets with a fixed data length, the demodulation circuit sets a speed for switching between L and H levels of a clock signal in such a manner that the speed for first data including a packet header to be embedded in a header section of the split TLV packets is twice the speed for data subsequent to the first data. The transmitting-side back-end processing circuit QAM-modulates a signal demodulated by the demodulation circuit for cable broadcasting purposes.

Low-noise block downconverter (LNB) of a satellite dish receives a request from a satellite broadcast signal receiver to transmit a signal for a channel to the receiver. If the channel requested by the receiver is different from a channel requested by another satellite broadcast signal receiver, the LNB in response provides a signal for the channel requested by the receiver at a frequency that is allocated to the receiver. If the channel requested by the receiver is the same as a channel requested by another satellite broadcast signal receiver, the LNB provides an instruction to the requesting receiver for the receiver to retune to the frequency used for the other satellite broadcast signal receiver. The requesting receiver can then receive the signal for said channel which is being provided by the LNB at the frequency used for the other satellite broadcast signal receiver.

Low-noise block downconverter (LNB) of a satellite dish receives a request from a satellite broadcast signal receiver to transmit a signal for a channel to the receiver. If the channel requested by the receiver is different from a channel requested by another satellite broadcast signal receiver, the LNB in response provides a signal for the channel requested by the receiver at a frequency that is allocated to the receiver. If the channel requested by the receiver is the same as a channel requested by another satellite broadcast signal receiver, the LNB provides an instruction to the requesting receiver for the receiver to retune to the frequency used for the other satellite broadcast signal receiver. The requesting receiver can then receive the signal for said channel which is being provided by the LNB at the frequency used for the other satellite broadcast signal receiver.

An information terminal with low power consumption is provided. The information terminal includes a liquid crystal element, a light-emitting element, a first transistor, and a touch sensor. The touch sensor includes a photodiode, a second transistor, and a third transistor. The first transistor has a function of controlling a current flowing through the light-emitting element. The photodiode is electrically connected to a gate of the third transistor through the second transistor. A gate of the first transistor is electrically connected to the gate of the third transistor through at least one transistor.

An information terminal with low power consumption is provided. The information terminal includes a liquid crystal element, a light-emitting element, a first transistor, and a touch sensor. The touch sensor includes a photodiode, a second transistor, and a third transistor. The first transistor has a function of controlling a current flowing through the light-emitting element. The photodiode is electrically connected to a gate of the third transistor through the second transistor. A gate of the first transistor is electrically connected to the gate of the third transistor through at least one transistor.

Disclosed is an apparatus and method of providing a high quality 360-degree VR image. A method of decoding a 360-degree VR image according to the present disclosure includes: receiving a bit stream including 360-degree VR image information; decoding information related to a 360-degree VR service from the bitstream; detecting a region of interest based on the information related to the 360-degree VR service; and providing to a user a 360-degree VR image for the region of interest.

Disclosed is an apparatus and method of providing a high quality 360-degree VR image. A method of decoding a 360-degree VR image according to the present disclosure includes: receiving a bit stream including 360-degree VR image information; decoding information related to a 360-degree VR service from the bitstream; detecting a region of interest based on the information related to the 360-degree VR service; and providing to a user a 360-degree VR image for the region of interest.

A semiconductor device system comprising a central controller and a plurality of hardware nodes. The hardware nodes are interconnected with each other through hard-wired connections which support the transmissions of globally asynchronous continuous-time binary value, CTBV, signals. There is defined a point-to-point(s) communication path between two hardware nodes which are processing nodes, along a sequence of hard-wired connections connected to each other through a switching circuitry. The switching circuitry is controlled by at least one hardware node which are communication node. The switching circuitry selectably connects, based on configuration data, two hard-wired connections in the sequence of hard-wired connections, to permit the transmission of each CTBV signal along the sequence of hard-wired connections. The at least one switching circuitry is latency-deterministic.

A semiconductor device system comprising a central controller and a plurality of hardware nodes. The hardware nodes are interconnected with each other through hard-wired connections which support the transmissions of globally asynchronous continuous-time binary value, CTBV, signals. There is defined a point-to-point(s) communication path between two hardware nodes which are processing nodes, along a sequence of hard-wired connections connected to each other through a switching circuitry. The switching circuitry is controlled by at least one hardware node which are communication node. The switching circuitry selectably connects, based on configuration data, two hard-wired connections in the sequence of hard-wired connections, to permit the transmission of each CTBV signal along the sequence of hard-wired connections. The at least one switching circuitry is latency-deterministic.