Patent classifications
H04L12/883
Guaranteed delivery in receiver side overcommitted communication adapters
Aspects of the invention include receiving an input/output (I/O) request that includes a data stream from a host processor. The receiving is at a network adapter of a storage controller that manages storage for the host processor. The storage controller includes a storage buffer to store data received from the host processor before migrating it to the storage. The storage controller also includes a data cache. It is determined whether the storage buffer has enough free space to store the received data stream. Based at least in part on determining that the storage buffer has enough free space to store the received data stream, the received data stream is stored by the network adapter in the storage. Based at least in part on determining that the storage buffer does not have enough free space to store the received data stream, the received data stream is stored in the data cache.
TRANSMIT POWER CONTROL
This disclosure describes systems, methods, and devices related to transmit power control (TPC). A device may identify a link measurement request frame from a first station device. The device may determine, for each transmit chain of the first station device, a TPC action to be performed by the first device. The device may cause to send a link measurement report frame comprising a value indicative of the TPC action for each transmit chain. The device may identify an acknowledgement from the first station device.
Apparatus and buffer control method thereof in a wireless communication system
A 5G communication system or pre-5G communication system for supporting a higher data rate than that of a beyond 4G communication system such as an LTE is provided. A method by an apparatus for controlling buffers in a wireless communication system comprises storing information related to a packet in at least one of a first buffer or a second buffer, transmitting data generated based on the packet, and, when an acknowledgement signal is received for the data, discarding the information.
Technologies for scalable network packet processing with lock-free rings
Technologies for network packet processing include a computing device that receives incoming network packets. The computing device adds the incoming network packets to an input lockless shared ring, and then classifies the network packets. After classification, the computing device adds the network packets to multiple lockless shared traffic class rings, with each ring associated with a traffic class and output port. The computing device may allocate bandwidth between network packets active during a scheduling quantum in the traffic class rings associated with an output port, schedule the network packets in the traffic class rings for transmission, and then transmit the network packets in response to scheduling. The computing device may perform traffic class separation in parallel with bandwidth allocation and traffic scheduling. In some embodiments, the computing device may perform bandwidth allocation and/or traffic scheduling on each traffic class ring in parallel. Other embodiments are described and claimed.
Instantaneous garbage collection of network data units
Approaches, techniques, and mechanisms are disclosed for reutilizing discarded link data in a buffer space for buffering data units in a network device. Rather than wasting resources on garbage collection of such link data when a data unit is dropped, the link data is used as a free list that indicates buffer entries in which new data may be stored. In an embodiment, operations of the buffer may further be enhanced by re-using the discarded link data as link data for a new data unit. The link data for a formerly buffered data unit may be assigned exclusively to a new data unit, which uses the discarded link data to determine where to store its constituent data. As a consequence, the discarded link data actually serves as valid link data for the new data unit, and new link data need not be generated for the new data unit.
Queue management method and apparatus
A queue management method and apparatus are disclosed. The queue management method includes: storing a first packet to a first buffer cell included in a first macrocell, where the first macrocell is enqueued to a first entity queue, the first macrocell includes N consecutive buffer cells, and the first buffer cell belongs to the N buffer cells; correcting, based on a packet length of the first packet, an average packet length in the first macrocell that is obtained before the first packet is stored, to obtain a current average packet length in the first macrocell; and generating, based on the first macrocell and the first entity queue, queue information corresponding to the first macrocell of the first macrocell in the first entity queue, a head pointer in the first macrocell, a tail pointer in the first macrocell, and the current average packet length in the first macrocell.
Flow Control Device and Method
A flow control device includes an analysis unit identifying a flow of a received packet, a plurality of queues temporarily storing packets sorted according to each flow, an allocation information storage unit storing allocation information regarding a queue allocated for each flow, a sorting unit deciding a queue to be a storage destination of the received packet and sorts the packet based on a result identified by the analysis unit and the allocation information, a saved packet holding unit saving a packet belonging to a flow determined to have no allocation information regarding the queue to be allocated by the sorting unit, and a transmission unit transmitting the packet temporarily stored in the plurality of queues and the packet saved in the saved packet holding unit to a processing unit that processes a packet.
PACKET PROCESSING METHOD AND RELATED DEVICE
A packet processing method and device are provided, to save CPU resources consumed by parsing a packet. The method includes: parsing, by an intelligent network interface card, a received first packet to obtain an identifier of the first packet; updating, by the intelligent network interface card, a control field of a first memory buffer based on the identifier of the first packet; storing, by the intelligent network interface card, a payload of the first packet or a packet header and a payload of the first packet into the first address space through DMA based on an aggregation position of the first packet; aggregating, by a host, the first address information and at least one piece of second address information based on an updated control field in the first mbuf; and reading, by a virtual machine, address information, to obtain data in an address space indicated by the address information.
EFFICIENT PACKET QUEUEING FOR COMPUTER NETWORKS
A method during a first cycle includes receiving, at a first port of a device, a plurality of network packets. The method may include storing, by the device, at least some portion of a first packet of the plurality of network packets at a first address within a first record bank and storing, by the device and concurrent with storing the at least some portion of the first packet from the first address, at least some portion of a second packet of the plurality of network packets at a second address within a second record bank, different than the first record bank. The method may further include storing, by the device, the first address within the first record bank and the second address within the second record bank in the first link stash associated with the first record bank and updating, by the device, a tail pointer to reference the second address.
Technologies for dynamic multi-core network packet processing distribution
Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.