H04L25/03853

WAVEFORM CORRECTION APPARATUS, WAVEFORM CORRECTION METHOD, AND INFORMATION PROCESSING SYSTEM

A waveform correction apparatus includes a receiver configured to receive a first signal and a second signal from a signal transmission apparatus, the first signal being a PAM4 signal having a data pattern of a bit array in which gray coding is performed, and the second signal being a PAM4 signal having a data pattern of a bit array in which the gray coding is not performed, and a processor coupled to the receiver and configured to adjust a number of taps in an equalizer based on a difference between correct count values of forward error correction performed on the respective data patterns of the first signal and the second signal.

Electronic circuit capable of selectively compensating for crosstalk noise and inter-symbol interference
10937488 · 2021-03-02 · ·

An electronic circuit including: a driver for outputting a driven first signal by driving a first signal among signals received in parallel; a selector circuit for selecting one of the first signal and a second signal among the signals received in parallel; and a compensator circuit for generating a first compensation signal for compensating the driven first signal, in response to the first signal or the second signal selected by the selector circuit, wherein, when the selector circuit selects the first signal, the compensator circuit generates the first compensation signal to compensate for an inter-symbol interference of the driven first signal, and wherein, when the selector circuit selects the second signal, the compensator circuit generates the first compensation signal to compensate for a crosstalk noise of the driven first signal caused by a driven second signal driven from the second signal.

BASE STATION FOR COMMUNICATING USING PLURALITY OF ANTENNAS AND OPERATION METHOD THEREFOR
20200412423 · 2020-12-31 ·

According to an embodiment of the disclosure, a base station communicating by using a plurality of antennas includes: a memory; a transceiver including the plurality of antennas forming an array structure; and at least one processor configured to convert first in-phase quadrature (IQ) data included in a first digital signal into radio frequency (RF) signals and then apply the RF signals to the plurality of antennas, respectively, detect a back-lobe signal beam-formed by the plurality of antennas, and perform linearization on second IQ data included in a second digital signal, based on the detected back-lobe signal.

Asymmetric factorization of generalized raised cosine filters for improved selectivity

An apparatus to transmit and receive wireless communications is disclosed in which the transmit circuitry includes a square root raised cosine filter to pulse shape modulate signals and the receive circuitry includes a higher order Nyquist receive filter coupled to receive the input signals and remove the pulse shaping modulation. The cascaded combination of the transmit and receive filters has a frequency response equivalent to a higher order generalized raised cosine filter response.

System with multiple virtual radio units in a radio unit that is remote from at least one baseband controller
10797734 · 2020-10-06 · ·

A communication system is provided. The communication system includes a at least one baseband controller configured to process signals in a baseband frequency band. The communication system also includes at least one radio unit that is physically remote from the at least one baseband controller. Each radio unit includes a plurality of virtual radio units (VRUs) in a physical housing of the respective radio unit. Each radio unit also includes a fronthaul interface configured to communicate with the at least one baseband controller using a packet-based protocol on behalf of each VRU. Each radio unit also includes at least one radio frequency front end unit configured to transmit from and receive on behalf of each of the VRUs.

RECEIVING APPARATUS AND RECEIVING METHOD
20200304350 · 2020-09-24 · ·

A receiving apparatus includes a first sample circuit configured to extract first binary data based on a first voltage and a clock timing of a received signal, a second sample circuit configured to extract second binary data based on an adjustable second voltage and a clock timing of the received signal, and a waveform processor configured to acquire a plurality of the second binary data from the second sample circuit using a pattern, the pattern corresponding to the first binary data extracted by the first sample circuit with consecutive sampling timings, determine an appearance frequency of the received signal based on the plurality of second binary data and the first binary data, and generate waveform information of the received signal according to the determined appearance frequency.

Dual-duplex link with asymmetric data rate selectivity
10778404 · 2020-09-15 · ·

A Serializer/Deserializer (SERDES) circuit is disclosed. The circuit includes an input/output (I/O) pad for coupling to a dual duplex SerDes link. A transmit circuit is coupled to the I/O pad, and includes transmit rate selection circuitry to select between data transmission at a full rate or a sub-rate. A receive circuit is coupled to the I/O pad, and includes receive rate selection circuitry to select between data receipt at the full rate or the sub-rate. Data transmitted by the transmit circuit is at a data rate different than data received by the receive circuit.

ELECTRONIC CIRCUIT CAPABLE OF SELECTIVELY COMPENSATING FOR CROSSTALK NOISE AND INTER-SYMBOL INTERFERENCE
20200243129 · 2020-07-30 ·

An electronic circuit including: a driver for outputting a driven first signal by driving a first signal among signals received in parallel; a selector circuit for selecting one of the first signal and a second signal among the signals received in parallel; and a compensator circuit for generating a first compensation signal for compensating the driven first signal, in response to the first signal or the second signal selected by the selector circuit, wherein, when the selector circuit selects the first signal, the compensator circuit generates the first compensation signal to compensate for an inter-symbol interference of the driven first signal, and wherein, when the selector circuit selects the second signal, the compensator circuit generates the first compensation signal to compensate for a crosstalk noise of the driven first signal caused by a driven second signal driven from the second signal.

EVENT-TRIGGERED WAVEFORM TYPE SELECTION

Methods, systems, and devices for wireless communications are described. The method may include a user equipment (UE) transmitting a first signal using a first waveform type. After transmitting the first signal using the first waveform type, the UE may identify a trigger event for waveform type switching by the UE and select a waveform type from among a set of waveform types based on identifying the trigger event. The UE may then transmit a second signal using the selected waveform type.

ADAPTIVE DIGITAL PRE-DISTORTION

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an apparatus may receive an indication of a selected digital pre-distortion (DPD) kernel from multiple DPD kernels. The apparatus may store multiple envelope values associated of with samples of an in-phase/quadrature (I/Q) signal and select a subset of envelope values based at least in part on the selected DPD kernel. The apparatus may generate, using the subset of envelope values and a look-up-table (LUT) component, an envelope computation value. The apparatus may store multiple computational values associated with the samples and select, based at least in part on the selected DPD kernel, at least one subset of computational values. The apparatus may generate an output sample that includes DPD based at least in part on combining the envelope computation value with the at least one subset of computational values. Numerous other aspects are described.