A computer-implemented method of estimating transmit symbol vectors transmitted in an overloaded communication channel includes receiving a signal represented by a received signal vector, the received signal vector corresponding to a superposition of signals representing transmitted symbols selected from a constellation of symbols and transmitted from one or more transmitters. Continuous first and second functions in a search space in a convex domain are defined. The first function and the second function are combined into a third function, and a fractional programming algorithm is applied to the third function, targeted to finding an input vector that minimizes the third function. A mapping rule translates the found input vector into an estimated transmit symbol vector, and the estimated transmit symbol vector is output to a decoder for decoding into an estimated transmit symbol from the constellation.

A computer-implemented method of estimating transmit symbol vectors transmitted in an overloaded communication channel includes receiving a signal represented by a received signal vector, the received signal vector corresponding to a superposition of signals representing transmitted symbols selected from a constellation of symbols and transmitted from one or more transmitters. Continuous first and second functions in a search space in a convex domain are defined. The first function and the second function are combined into a third function, and a fractional programming algorithm is applied to the third function, targeted to finding an input vector that minimizes the third function. A mapping rule translates the found input vector into an estimated transmit symbol vector, and the estimated transmit symbol vector is output to a decoder for decoding into an estimated transmit symbol from the constellation.

In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

Millimeter-wave (mmWave) and sub-mmWave technology, apparatuses, and methods that relate to transceivers and receivers for wireless communications are described. The various aspects include an apparatus of a communication device including one or more antennas configured to receive an RF signal and an ADC system. The ADC system includes a 1-bit ADC configured to receive the RF signal, and an ADC controller circuitry configured to measure a number of positive samples in the received RF signal for a plurality of thresholds of the 1-bit ADC, estimate receive signal power associated with the received RF signal based on the measured number of positive samples, determine a direct current(DC) offset in the received RF signal using the estimated received signal power, and adjust the received RF signal based on the determined DC offset.

The present disclosure provides a method for transmitting and receiving in a wireless communication system and an apparatus therefore. Specifically, in a wireless communication system according to an embodiment of the present disclosure, there is provided a method for transmitting and receiving a signal by a receiving apparatus, the method includes receiving, from a transmitting apparatus, signals modulated based on a differential phase shift keying (DPSK) method through a plurality of reception paths, calculating a differential value in each reception path of the plurality of reception paths based on the received signals, and calculating reliability for the received signals, in which the reliability is proportional to a real value of a sum of the differential values in each reception path of the plurality of reception paths.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

A receiver converter circuit included in a computer system may receive multiple signals that encode a serial data stream that encode multiple data symbols. To correct for baseline wander, the receiver circuit may generate a disparity signal that is used to control the application of a differential voltage to the multiple signals. The receiver circuit may also employ the disparity signal to generate a gradient against which the magnitude of differential voltage is calibrated.

A receiver converter circuit included in a computer system may receive multiple signals that encode a serial data stream that encode multiple data symbols. To correct for baseline wander, the receiver circuit may generate a disparity signal that is used to control the application of a differential voltage to the multiple signals. The receiver circuit may also employ the disparity signal to generate a gradient against which the magnitude of differential voltage is calibrated.

A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device.