An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

An interference suppression module for an Ethernet transceiver, the interference suppression module comprising circuitry configured to: receive a receiver output from a receiver module of the Ethernet transceiver, the receiver module configured to output a logic-high when a received voltage signal is higher than a receiver threshold, and output a logic-low when the received voltage signal is lower than the receiver threshold; receive an energy detection output from an energy detection module of the Ethernet transceiver, the energy detection module configured to output a logic-high when the received voltage signal is higher than a positive energy detection threshold or lower than a negative energy detection threshold, and output a logic-low when the received voltage signal is between the positive and negative energy detection thresholds; and output a predefined logic state to a receive pin of the Ethernet transceiver when the energy detection output is a logic-low.

One example includes a communication system. The system includes a data transmitter configured to generate a digital communication signal and a data receiver configured to receive the digital communication signal. The system also includes a pulse-width distortion (PWD) correction circuit arranged between the data transmitter and the data receiver and being configured to adjust at least one timing parameter associated with the communication signal.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

A computing apparatus, includes a first apparatus and a second apparatus, a differential transmission line that couples the first apparatus and the second apparatus to each other, a noise application unit that applies noise to the differential transmission line, a noise control unit that controls the noise application unit, and a margin measurement unit that measures an occurrence frequency of communication error between the first apparatus and the second apparatus.

A transceiver to communicate in a vehicle via a single twisted-pair Ethernet cable includes a transmitter to transmit signals via the single twisted-pair Ethernet cable and a receiver to receive signals via the single twisted-pair Ethernet cable. The transceiver includes an equalizer, a signal-to-noise ratio estimator, and a controller. The equalizer includes a notch filter and a slicer. The equalizer receives an input signal received by the transceiver via the single twisted-pair Ethernet cable. The notch filter cancels electromagnetic interference from the input signal and to output a filtered signal. The slicer slices the filtered signal. The signal-to-noise ratio estimator estimates a signal-to-noise ratio based on an output of the slicer. The controller controls a rate of adapting the equalizer by controlling a rate of change of tap values of the notch filter based on the signal-to-noise ratio.

An integrated circuit is disclosed and includes an Ethernet physical layer (PHY) with a plurality of communication channels. The communication channels coupled to a corresponding plurality of terminals. The integrated circuit further includes a plurality of electrical isolation circuits and a compensation circuit. At least one of the plurality of electrical isolation circuits is coupled to a corresponding one of the plurality of communication channels and electrically isolates the PHY from a corresponding one of the plurality of terminals. The compensation circuit is configured to compensate for at least one of baseline wander and parameter drift associated with at least one of the plurality of isolation circuits. The PHY and the plurality of isolation circuits are integrated on a single substrate.

A bidirectional isolated communication circuit and method for a differential signal. The circuit comprises a first detection circuit used for receiving a first differential pair from a first direction, converting the first differential pair into a first level signal, and inhibiting common-mode interference; a second detection circuit used for receiving a second differential pair from a second direction, converting the second differential pair into a second level signal, and inhibiting common-mode interference; an isolation adjustment circuit used for being provided between the first detection circuit and the second detection circuit and performing communication isolation; and a watchdog circuit used for being awoken according to the first differential pair and/or the second differential pair, and enabling the bidirectional isolated communication circuit to enter from a small current working mode to a normal working mode to perform communication isolation.