Methods, systems, and devices for wireless communications are described. A transmitting device may encode a set of bits to transmit to a receiving device based on a repetition factor. The transmitting device may map, based on the repetition factor, the set of encoded bits to a subset of subcarriers such as adjacent subcarriers of a set of subcarriers. The transmitting device may generate a signal including the set of encoded bits based on the mapping, and transmit the generated signal to the receiving device. The receiving device may receive a modulated signal from the transmitting device, and identify, based on a repetition factor, a subset of subcarriers including adjacent subcarriers of a set of subcarriers associated with the modulated signal. The receiving device may average the subset of subcarriers including the adjacent subcarriers, and demodulate the modulated signal in accordance with the averaged subset of subcarriers including the adjacent subcarriers.

A user equipment (910) is provided for use in a cellular network. The user equipment includes a transceiver (1010), a processor (1020), and a memory (1030). The user equipment (910) is configured to determine, for a data transmission, a mapping form a demodulation reference signal (DMRS) to a PNT-RS. A DMRS resulting signal is generated from a subset of DMRS for a first resource element in a subcarrier. The DMRS resulting signal is copied from the first resource element to a second resource element assigned to the PNT-RS in the subcarrier. The data transmission is transmitted using the DMRS resulting signal and the PNT-RS.

Certain disclosed methods, apparatus, and systems enable improved communication on a multiphase communication link through improved encoding techniques and protocol. A data communication apparatus has a plurality of line drivers configured to couple the apparatus to a 3-wire link, and a data encoder configured to encode at least 3 bits of binary data in each transition between two symbols that are consecutively transmitted by the plurality of line drivers over the 3-wire link such that each pair of consecutively-transmitted symbols comprises two different symbols. Each symbol defines signaling states of the 3-wire link during an associated symbol transmission interval such that each wire of the 3-wire link is in a different signaling state from the other wires of the 3-wire link during the associated symbol transmission interval. Data may be encoded using a combination of 3-phase and pulse amplitude modulation.

Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system that may include a telecommunications satellite. Embodiments include “chained” feedback-regulated voltage supply circuits. These circuits substantially eliminate the need for separate regulator circuits for each regulated voltage. These circuits are designed to automatically maintain a substantially constant first voltage at a first node for a first load and maintain a substantially constant second voltage at a second node for a second load. Some disclosed configurations of these circuits may be useful to achieve greater current capability at the same voltage without requiring larger switches and higher inductor and capacitor sizes that may be needed in a single (conventional) stage voltage supply circuit.

An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

A system having a set of common hardware and common signal processing together with a common waveform family that can be used to achieve both efficient radar and efficient communications functions. The system includes a common radar/communications transmitter having a transmission antenna and a combined radar and communications receiver having a common reception antenna. The common radar/communications transmitter is configured to transmit combined radar/communications waveform-modulated signals comprising symbols, each symbol consisting of an up chirp and a down chirp. The combined radar and communications receiver includes a baseband radar signal processing module configured to estimate range and range rate of a radar object from the received symbols and a baseband communications signal processing module configured to detect slopes and initial phases of the up and down chirps of each received symbol.

An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

Certain disclosed methods, apparatus, and systems enable improved communication on a multiphase communication link through improved encoding techniques and protocol. A data communication apparatus has a plurality of line drivers configured to couple the apparatus to a 3-wire link, and a data encoder configured to encode at least 3 bits of binary data in each transition between two symbols that are consecutively transmitted by the plurality of line drivers over the 3-wire link such that each pair of consecutively-transmitted symbols comprises two different symbols. Each symbol defines signaling states of the 3-wire link during an associated symbol transmission interval such that each wire of the 3-wire link is in a different signaling state from the other wires of the 3-wire link during the associated symbol transmission interval. Data may be encoded using a combination of 3-phase and pulse amplitude modulation.

Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system that may include a telecommunications satellite. Embodiments include chained feedback-regulated voltage supply circuits. These circuits substantially eliminate the need for separate regulator circuits for each regulated voltage. These circuits are designed to automatically maintain a substantially constant first voltage at a first node for a first load and maintain a substantially constant second voltage at a second node for a second load. Some disclosed configurations of these circuits may be useful to achieve greater current capability at the same voltage without requiring larger switches and higher inductor and capacitor sizes that may be needed in a single (conventional) stage voltage supply circuit.

Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system (550) that may include a telecommunications satellite. Embodiments generate a dynamic input bias signal based upon an information signal envelope (which may be pre-distorted) which is applied to the signal input of a power amplifier (PA), thus reducing average power consumption. Other embodiments further include dynamic linearization (518) of the information signal, and/or variation of the supply voltage to the power amplifier (PA) as a function of the envelope of the information signal. Another aspect is a multi-stage chained feedback regulated voltage supply circuit for providing two or more output voltages that may be used as alternative supply voltages to a power amplifier (PA).