A cluster correlator may be configured with: a first stage comprising a set of first correlators to correlate samples of an input signal with a first predetermined pattern and output an output sample, the set of first correlators to output a sample cluster corresponding to the output sample of the set of first correlators during a switching cycle of the first stage; a filter coupled to an output of the first stage to receive the sample cluster and to produce a processed output sample based on the sample cluster; and a second stage comprising at least one second correlator to receive a processed output sample from the filter and correlate the processed output sample with a second predetermined pattern, and output one or more correlation outputs during a switching cycle of the second stage.

A device includes a frequency offset (FO) compensation circuit coupled with a decoder, and a soft information measurement circuit. The frequency offset compensation circuit is configured to: (i) receive a continuous phase modulation (CPM) signal, (ii) adjust the CPM signal in a sampling window based on a frequency offset compensation value, and (iii) provide the adjusted CPM signal to the decoder. The decoder is configured to: (i) receive the adjusted CPM signal generated by the FO compensation circuit, (ii) decode the adjusted CPM signal to obtain one or more information symbols associated with the CPM signal, (iii) provide the one or more information symbols for soft information generation; and (iv) receive soft information provided by the soft information measurement circuit.

A method to receive telemetry messages over an RF channel, the method implemented by a system on a chip, in which a signal is received from the output of an input RF module, the received signal is offset in time and frequency wherein the signal, at first, is offset in time so that the offset magnitudes uniformly fill the length of one data bit, then, the signal is offset in frequency so that the offset magnitudes uniformly fill the space between the Fourier transform subcarriers, with the frequency offsets being independent of the time offsets; each signal processed at the preceding step is subjected to sequential Fourier transforms, with the first time element of each next transform immediately following the last element of the preceding transform; all messages are demodulated independently. The technical result consists in that messages can be received over multiple channels at multiple rates.

Described is a method of searching of multichannel signal and technique of demodulating and detecting DBPSK frequency division multiple access (FDMA) ultra-narrow band signal. A search is based on algorithm encompassing a signal-processing signal, and technique to demodulate and detect FDMA ultra-narrow band together with a method to increase time-frequency resolution.

A demodulator including a peak sampler to control an ADC or a digital resampler to sample a carrier signal in an unmodulated state at peaks, and to sample the carrier signal in a modulated state at a phase of the unmodulated state; and an envelope builder to determine an envelope signal based on differentials between maximum and minimum peaks of respective cycles of the sampled carrier signal. Further, a demodulator having an offset estimator to estimate in-phase and quadrature components of a carrier signal in an unmodulated state to determine in-phase and quadrature component offsets; a load modulated signal estimator to estimate in-phase and quadrature components of a load modulated signal by removing the in-phase and quadrature component offsets from in-phase and quadrature component samples of the carrier signal; and an envelope builder to build an envelope signal by combining the in-phase and quadrature components of the load modulated signal.

A method allowing a receiver device of a wireless communication system to receive a useful signal emitted by an emitter device. The useful signal corresponding to a signal, the phase or frequency of which is modulated by a sequence of two-state symbols corresponding to a sequence of binary data. A temporal envelope of the useful signal is detected and compared to a preset threshold value. Transitions between consecutive useful-signal symbols are detected, on the basis of the result of the comparison. A sequence of binary data is extracted from the useful signal depending on the detected transitions.

An embodiment of the present invention relates to an ultra low power wideband asynchronous binary phase shift keying (BPSK) demodulation method and a circuit configuration thereof. The ultra low power wideband asynchronous BPSK demodulation circuit comprises a sideband division and upper sideband signal delay unit dividing a modulated signal into an upper sideband and a lower sideband by a first order high-pass filter and a first order low-pass filter; a data demodulation unit latching, through a hysteresis circuit, a signal generated by a difference between the analog signals in which a phase difference between the delayed upper sideband analog signal and the lower sideband analog signal is aligned at 0, so as to demodulate digital data; and a data clock recovery unit for generating a data clock by using a signal digitalized from the lower sideband analog signal through a comparator and a data signal.

An embodiment of the present invention relates to an ultra low power wideband asynchronous binary phase shift keying (BPSK) demodulation method and a circuit configuration thereof. The ultra low power wideband asynchronous BPSK demodulation circuit comprises a sideband division and upper sideband signal delay unit dividing a modulated signal into an upper sideband and a lower sideband by a first order high-pass filter and a first order low-pass filter; a data demodulation unit latching, through a hysteresis circuit, a signal generated by a difference between the analog signals in which a phase difference between the delayed upper sideband analog signal and the lower sideband analog signal is aligned at 0, so as to demodulate digital data; and a data clock recovery unit for generating a data clock by using a signal digitalized from the lower sideband analog signal through a comparator and a data signal.