A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memory device stores a middle part of the FIFO queue, the middle part comprising a LL elements following, in an order, the head part and preceding, in the order, the tail part. A queue controller retrieves LL elements in the head part from the first memory device, moves LL elements in the middle part from the second memory device to the head part in the first memory device prior to the head part becoming empty, and updates LL parameters corresponding to the moved LL elements to indicate storage of the moved LL elements changing from the second memory device to the first memory device.

Systems and methods for flowlet switching using memory instructions. One embodiment is a method of distributing packets over multiple paths. The method includes determining an elapsed time between a packet and a previous packet. The method further includes, in response to determining that the elapsed time is less than an inter-packet gap threshold: retaining a previously selected path value indicated in the flow record, and providing the previously selected path value to the processing thread for transmitting the packet over a previously selected path associated with the previous packet. The method also further includes, in response to determining that the elapsed time is greater than the inter-packet gap threshold: updating the flow record by replacing the previously selected path value with the path value of the selected path of the memory instruction, and providing the path value to the processing thread for transmitting the packet over the selected path.

Systems and methods for flowlet switching using memory instructions. One embodiment is a method of distributing packets over multiple paths. The method includes determining an elapsed time between a packet and a previous packet. The method further includes, in response to determining that the elapsed time is less than an inter-packet gap threshold: retaining a previously selected path value indicated in the flow record, and providing the previously selected path value to the processing thread for transmitting the packet over a previously selected path associated with the previous packet. The method also further includes, in response to determining that the elapsed time is greater than the inter-packet gap threshold: updating the flow record by replacing the previously selected path value with the path value of the selected path of the memory instruction, and providing the path value to the processing thread for transmitting the packet over the selected path.

Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.

Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.

A routing system may include a primary message group to be used for synchronizing stored information. The primary message group may include multiple primary network devices. The multiple primary network devices may be configured with a first configuration regarding synchronizing the stored information. The primary message group may form a ring network topology. The routing system may include a secondary message group to be used for synchronizing the stored information. The secondary message group may include a single primary network device, of the multiple primary network devices, and multiple secondary network devices. Each secondary network device, of the multiple secondary network devices, may be included in a single secondary message group. The multiple secondary network devices may be configured with a second configuration regarding synchronizing the stored information. The secondary message group may form a different ring network topology.

Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A memory is coupled to the ports and configured to contain both respective input buffers allocated to the ingress ports and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to monitor an overall occupancy level of the memory, and when a data packet is received through an ingress port having an input buffer that is fully occupied while the overall occupancy level of the memory is below a specified maximum, to allocate additional space in the memory to the input buffer and to accept the received data packet into the additional space.

The present disclosure provides a structured, pipelined large time-space switch and method of operation resolving interconnect complexity. The time-space switch results in an interconnect complexity that does not grow as the spatial dimension is increased and results in a reduction of long high fan-out nets, a quicker layout, and improved clock speed. With respect to time-space switch fabric implementation, the present invention improves the maximum clock frequency of the switch fabric, and improves integrated circuit layout time by eliminating long high fan-out nets. Certain high-speed large switch fabrics may not be realizable without this implementation, and it significantly reduces implementation time (and cost). The present invention may include link encoding of switch frames by mapping 8B10B control characters into an 64B65B format (similar to Generic Framing Protocol-Transparent (GFP-T)), wrapping 32 65B encoded words with an 11-bit error correcting code, and scrambling the frame with a frame synchronous scrambler.

Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.

Disclosure is made of a shared memory switch and methods and system for controlling such. The shared memory switch may allocate cells in a storage array to respective use cases, the use cases including input buffering, output queuing, free cell allocation, and retry buffering. A set of data packets may be stored in the cells allocated to output queuing, wherein each cell allocated to output queuing stores a respective data packet of the set of data packets. A subset of the set of data packets may be transmitted to a destination external to the shared memory switch. The cells storing the subset of data packets may be reallocated to the retry buffering use case, wherein cells allocated to retry buffering use case are a retry buffer.