An asynchronous switching system and method for processing SDI data streams, the system and method utilizing one or more buffers for cleaning up an output of a dirty IP switch.

An asynchronous switching system and method for processing SDI data streams, the system and method utilizing one or more buffers for cleaning up an output of a dirty IP switch.

An interconnect apparatus performs real time scoring and data throughput measurement of parallel data channels. The scoring and measurement information is communicated as feedback across the interconnect. Processing circuitry in the interconnect apparatus routes data to channels that have the best performance and reduces the data rate on channels that have lower performance based on the feedback information. This provides a method of dynamic load balancing to achieve optimal video data rates in a dynamic impedance environment. The interconnect apparatus also adjusts phase and data sampling times for improved fidelity of data transported across the interface.

A system for transporting fast frame rate video data from a high frame rate image sensor mosaics and spreads the fast frame rate video data in 19201080p30 video frames for transporting via an existing standard video architecture. Packing information, spreading information, and unique ID/timestamps for each frame is encoded in metadata and inserted in ancillary metadata space of the 1080p30 video frames. A robust encoding scheme generates the metadata and ensures that the transported video can be reassembled into its original fast frame rate form after being spread over multiple channels.

Disclosed are a bitstream alignment and synchronous processing method, transmitting terminal, receiving terminal and communication system. The method includes: configuring, when multiple bitstreams are required to be aligned, by a transmitting terminal, alignment auxiliary information in the multiple bitstreams so as to store the same or transmit the same to a receiving terminal; and acquiring, by the receiving terminal, the multiple bitstreams, and synchronizing each of the bitstreams of a different standard according to the alignment auxiliary information carried in each of the bitstreams.

There is provided a device comprising a non-transitory memory storing an executable code, a hardware processor executing the executable code to receive Internet protocol (IP) packets encapsulating a video content, the IP packets including a frame having a header storing header information relating to the video content, retrieve at least one portion of the header information relating to the video content from the header, retrieve the video content from the IP packets, prepare the retrieved video content for transmission using serial digital interface (SDI) protocol, insert the at least one portion of the header information into at least one of a vertical ancillary (VANC) data space and a horizontal ancillary (HANC) data space of the prepared video content using the SDI protocol, and transmit the prepared video content using the SDI protocol, including the at least one portion of the header information in the VANC space.

An information processing apparatus for reproducing second content in synchronization with reproduction of first content by a second information processing apparatus different from the information processing apparatus, the first content comprising audio content. The information processing apparatus comprising circuitry configured to: extract a first feature from the audio content; obtain a second feature of the audio content, the second feature being together with the second content; compare the first feature with the second feature; and generate, based on results of the comparing, synchronization information used for reproducing the second content in synchronization with the first content.

An interconnect apparatus performs real time scoring and data throughput measurement of parallel data channels. The scoring and measurement information is communicated as feedback across the interconnect. Processing circuitry in the interconnect apparatus routes data to channels that have the best performance and reduces the data rate on channels that have lower performance based on the feedback information. This provides a method of dynamic load balancing to achieve optimal video data rates in a dynamic impedance environment. The interconnect apparatus also adjusts phase and data sampling times for improved fidelity of data transported across the interface.

The system can utilize a standard high speed FPGA interface for a non-traditional use to facilitate the processing of high amounts of streaming digital data or the method can be implemented in other high speed data transfer systems. This system and method include the use of training/calibration pattern techniques implemented in a FPGA, or other system, to calibrate numerous multi-arm demultiplexers. The training/calibration sequence data rate being slower than the input data rate. In one example, the system and method utilized a mono-bit receiver capable of digitizing signals of at least 40 GHz with at least 20 GHz of instantaneous bandwidth.

The system can utilize a standard high speed FPGA interface for a non-traditional use to facilitate the processing of high amounts of streaming digital data or the method can be implemented in other high speed data transfer systems. This system and method include the use of training/calibration pattern techniques implemented in a FPGA, or other system, to calibrate numerous multi-arm demultiplexers. The training/calibration sequence data rate being slower than the input data rate. In one example, the system and method utilized a mono-bit receiver capable of digitizing signals of at least 40 GHz with at least 20 GHz of instantaneous bandwidth.