An image sensor includes a pixel defining pattern in a mesh form. A first division pattern divides a pixel area into two halves. A second division pattern divides the pixel area into two halves. A first diagonal division pattern divides the pixel area into two halves. A second diagonal division pattern divides the pixel area into two halves. First through eighth photodiodes are arranged in the pixel area.

An image sensor includes a pixel defining pattern in a mesh form. A first division pattern divides a pixel area into two halves. A second division pattern divides the pixel area into two halves. A first diagonal division pattern divides the pixel area into two halves. A second diagonal division pattern divides the pixel area into two halves. First through eighth photodiodes are arranged in the pixel area.

The present disclosure relates to a solid state image sensor and electronic equipment that enable degradation in image quality of a captured image to be suppressed even if any pixel in a pixel array is configured as a functional pixel for obtaining desired information in order to obtain information different from a normal image. In a plurality of pixels constituting subblocks provided in an RGB Bayer array constituting a block which is a set of color units, normal pixels that capture a normal image are arranged longitudinally and laterally symmetrically within the subblock, and functional pixels for obtaining desired information other than capturing an image are arranged at the remaining positions. The present disclosure can be applied to a solid state image sensor.

An electronic device includes a first transistor, a second transistor, and a sensing circuit coupled to at least one of the first transistor and the second transistor. The sensing circuit includes a diode, a third transistor, and a fourth transistor. The diode has a first terminal. The third transistor has a first terminal and a second terminal. The first terminal of the third transistor is coupled to the first terminal of the diode. The fourth transistor has a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to a data driver.

Some embodiments relate to an imaging system including an active pixel and an analog-to-digital conversion (ADC) circuit including comparator. The comparator may be operatively coupled to the active pixel and configured to receive an output of the active pixel. The back-end ADC and memory circuit may be operatively coupled to the active pixel. The back-end ADC and memory circuit may include a write control circuit, an ADC memory operatively coupled to a read/write data bus and to the write control circuit, and a state latch operatively coupled to the write control circuit.

An electrical device includes: a camera assembly that includes an image sensor configured to capture an image of an object and to generate color image data, wherein the image sensor has the green element blocks, the blue element blocks, and the red element blocks arranged in an array of the Bayer format at each pixel position in order to generate color image data, the green element blocks, the blue element blocks, and the red element blocks includes Multiple physical pixel elements respectively, the green element block includes two green physical pixel elements and two white physical pixel elements, the blue element block includes two blue physical pixel elements and two white physical pixel elements, and the red element block includes two red physical pixel elements and two white physical pixel elements; and a main processor that performs image process.

An electrical device includes: a camera assembly that includes an image sensor configured to capture an image of an object and to generate color image data, wherein the image sensor has the green element blocks, the blue element blocks, and the red element blocks arranged in an array of the Bayer format at each pixel position in order to generate color image data, the green element blocks, the blue element blocks, and the red element blocks includes Multiple physical pixel elements respectively, the green element block includes two green physical pixel elements and two white physical pixel elements, the blue element block includes two blue physical pixel elements and two white physical pixel elements, and the red element block includes two red physical pixel elements and two white physical pixel elements; and a main processor that performs image process.

Provided are an image sensor, an imaging apparatus, and a signal processing method. The image sensor includes a filter array, a pixel array, and a processing circuit. The filter array includes a plurality of filter regions each including a plurality of filter units. The processing circuit is configured to: combine the electrical signals generated by the pixels corresponding to each filter unit for outputting as a combined luminance value and forming a first intermediate image; generate a first color signal, a second color signal, and a third color signal based on the electrical signals generated by the pixels corresponding to each filter region; and process the first color signal, the second color signal, and the third color signal to obtain a plurality of second intermediate images representing chrominance values of the filter region, and fuse the first intermediate image and the second intermediate images to obtain a first target image.

A time-of-flight (ToF) image sensor system includes a pixel array, where each pixel of the pixel array is configured to receive a reflected modulated light signal and to demodulate the reflected modulated light signal to generate an electrical signal; a plurality of analog-to-digital converters (ADCs), where each ADC is coupled to at least one assigned pixel of the pixel array and is configured to convert a corresponding electrical signal generated by the at least one assigned pixel into an actual pixel value; and a binning circuit coupled to the plurality of ADCs and configured to generate at least one interpolated pixel, where the binning circuit is configured to generate each of the at least one interpolated pixel based on actual pixel values corresponding to a different pair of adjacent pixels of the pixel array, each of the at least one interpolated pixel having a virtual pixel value.

Solid-state imaging elements are disclosed. In one example, an upstream circuit block generates a predetermined reset level and a plurality of signal levels each corresponding to an exposure amount, and causes capacitive elements, different from each other, to hold them. A selection circuit sequentially performs control to connect the capacitive element in which the reset level is held to a predetermined downstream node, control to disconnect capacitive elements from the downstream node, and control to connect the capacitive element in which any of the plurality of signal levels is held to the downstream node. A downstream reset transistor initializes a level of the downstream node when the capacitive elements are disconnected from the downstream node. A downstream circuit sequentially reads the reset level and the plurality of signal levels via the downstream node