Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a plurality of insulating layers spaced apart from each other in a stacking direction, a slit insulating layer passing through the plurality of insulating layers, a plurality of first variable resistance layers alternately disposed with the plurality of insulating layers in the stacking direction, a plurality of conductive lines interposed between the slit insulating layer and the plurality of first variable resistance layers and alternately disposed with the plurality of insulating layers in the stacking direction, a conductive pillar passing through the plurality of insulating layers and the plurality of first variable resistance layers, and a second variable resistance layer surrounding a sidewall of the conductive pillar.

A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.

A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.

A variable resistance memory device includes a stacking pattern disposed on a substrate, a vertical structure extends in a first direction, which is perpendicular to a top surface of the substrate, and penetrates the stacking pattern, and a horizontal conductive line disposed adjacent to the stacking pattern and extending in a second direction that is parallel to the top surface of the substrate. The vertical structure includes a vertical conductive line penetrating the stacking pattern, a variable resistance element enclosing the vertical conductive line, and a selection element interposed between the vertical conductive line and the variable resistance element. Each of the vertical conductive line, the variable resistance element, and the selection element extends in the first direction. The stacking pattern is electrically connected to the horizontal conductive line and extends along the horizontal conductive line and in the second direction.

A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

A variable resistance memory device including a substrate; horizontal structures spaced apart from each other in a first direction perpendicular to a top surface of the substrate; variable resistance patterns on the horizontal structures, respectively; and conductive lines on the variable resistance patterns, respectively, wherein each of the horizontal structures includes a first electrode pattern, a semiconductor pattern, and a second electrode pattern arranged along a second direction parallel to the top surface of the substrate, and each of the variable resistance patterns is between one of the second electrode patterns and a corresponding one of the conductive lines.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.