A fuse blowing method is disclosed. The fuse blowing method includes the following operations: receiving a number signal, in which the number signal includes a number; triggering the number of several fuse pumps according to the number signal; and generating a current to blow a fuse.

An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

A high-performance and highly reliable semiconductor device is provided. The semiconductor device includes: a first oxide; a source electrode; a drain electrode; a second oxide over the first oxide, the source electrode, and the drain electrode; a gate insulating film over the second oxide; and a gate electrode over the gate insulating film. The source electrode is electrically connected to the first oxide. The drain electrode is electrically connected to the first oxide. Each of the first oxide and the second oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. Each of the first oxide and the second oxide includes more In atoms than element M atoms. An atomic ratio of the In, the Zn, and the element M in the first oxide is equal to or similar to an atomic ratio of the In, the Zn, and the element M in the second oxide.

A nonvolatile memory device may include a substrate, a plurality of gate electrodes stacked on the substrate, a first conductive pillar that extends in a first direction and intersects the gate electrodes, a second conductive pillar that extends in the first direction and intersects the gate electrodes, the second conductive pillar being spaced apart from the first conductive pillar, an information storage film between the first conductive pillar and each of the gate electrodes and between the second conductive pillar and each of the gate electrodes, the information storage film including chalcogenide, a conductive layer spaced apart from the gate electrodes in the first direction, a first charge dissipation layer between the first conductive pillar and the conductive layer, and a second charge dissipation layer between the second conductive pillar and the conductive layer, the second charge dissipation layer being spaced apart from the first charge dissipation layer.

A three-dimensional memory device includes a base dielectric layer disposed on a substrate, a stack structure that includes word lines and interlayer dielectric layers that are alternately stacked on the base dielectric layer, a bit line that penetrates the stack structure and extends in a vertical direction perpendicular to a top surface of the substrate, and buried storage patterns interposed between the bit line and the word lines and spaced apart from each other in the vertical direction. Each of the buried storage patterns has a width in a horizontal direction parallel to the top surface of the substrate. The widths of the buried storage patterns increase with increasing vertical distance from the substrate.

A memory device includes: first conductive lines extending in a first horizontal direction on a substrate; second conductive lines extending on the first conductive lines in a second horizontal direction; third conductive lines extending on the second conductive lines in the first horizontal direction; first memory cells provided at portions where the first conductive lines cross the second conductive lines; second memory cells provided at portions where the second conductive lines cross the third conductive lines; first dummy patterns horizontally spaced apart from the first memory cells and the second memory cells; and second dummy patterns horizontally spaced apart from the first memory cells and the second memory cells, the second dummy patterns facing the first dummy patterns, respectively, in the second horizontal direction. The plurality of first dummy patterns and the plurality of second dummy patterns are on different vertical levels from each other.

A memory device includes an ovonic memory element. The ovonic memory element contains a first electrode, a second electrode, and an ovonic threshold switching material portion located between the first electrode and the second electrode. A first surface of the first electrode that contacts a first surface of the ovonic threshold switching material portion has a greater area than a first surface of the second electrode that contacts a first segment of a second surface of the ovonic threshold switching material portion.

A computational device includes a phase-change material (PCM) variable microelectromechanical systems (MEMS) capacitor and a power source. The PCM variable MEMS capacitor includes a substrate, a first electrode, a second electrode, a PCM, and a heater. The first electrode is spaced apart from the substrate to define a PCM cavity. The second electrode is spaced apart from the first electrode to define a capacitance gap. The PCM is disposed within the PCM cavity. The heater element is coupled to receive a voltage pulse, whereby a temperature of the PCM varies to thereby vary the capacitance gap. The power source is coupled to the PCM variable MEMS capacitor and is operable to (i) supply the voltage pulse to the heater and (ii) a time-dependent voltage between the first electrode and the second electrode, to thereby implement a single multiply operation.

Provided is a semiconductor memory device including: cell blocks, each including a folding structure in which electrode structures and insulating structures are alternately provided, wherein the electrode structures and the insulating structures extend in a vertical direction and are connected with each other so as to have at least two U-shaped structures forming villus shapes in a plan view, the electrode structures include a vertical electrode and a switching material layer, and the cell blocks are provided in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction; and a gate stack structure including gate electrodes and interlayer insulating layers that are alternately stacked in the vertical direction along sidewalls of the electrode structures.

An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.