A semiconductor device and a method for producing thereof is provided. The semiconductor device includes a plurality of device cells, each comprising a body region, a source region, and a gate electrode adjacent to the body region and dielectrically insulated from the body region by a gate dielectric; and an electrically conductive gate layer comprising the gate electrodes or electrically connected to the gate electrodes of the plurality of device cells. The gate layer is electrically connected to a gate conductor and includes at least one of an increased resistance region and a decreased resistance region.

A lateral p-n diode in the center of and surrounded by a vertical Silicon-Controlled Rectifier (SCR) forms an Electro-Static-Discharge (ESD) protection structure. The lateral p-n diode has a cross-shaped P+ diode tap with four rectangles of N+ diode regions in each corner of the cross. A P-well under the P+ diode tap is also an anode of a vertical PNPN SCR that has a deep N-well in a P-substrate. The deep N-well surrounds the lateral diode. Triggering MOS transistors are formed just beyond the four ends of the cross shaped P+ diode tap. Each triggering MOS transistor has N+ regions at the edge of the deep N-well and in the P-substrate that act as the cathode terminals. A deep P+ implant region under the N+ region at the edge of the deep N-well decreases a trigger voltage of the vertical SCR.

A lateral p-n diode in the center of and surrounded by a vertical Silicon-Controlled Rectifier (SCR) forms an Electro-Static-Discharge (ESD) protection structure. The lateral p-n diode has a cross-shaped P+ diode tap with four rectangles of N+ diode regions in each corner of the cross. A P-well under the P+ diode tap is also an anode of a vertical PNPN SCR that has a deep N-well in a P-substrate. The deep N-well surrounds the lateral diode. Triggering MOS transistors are formed just beyond the four ends of the cross shaped P+ diode tap. Each triggering MOS transistor has N+ regions at the edge of the deep N-well and in the P-substrate that act as the cathode terminals. A deep P+ implant region under the N+ region at the edge of the deep N-well decreases a trigger voltage of the vertical SCR.

A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F.sup.2. This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.

A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.

A device, including: a first structure including first memory cells, the first memory cells including first transistors; and a second structure including second memory cells, the second memory cells including second transistors, where the second transistors overlay the first transistors, and a plurality of memory cells control lines, where the first transistors are self-aligned to the second transistors, where a second transistor channel of the second transistors is aligned to a first transistor channel of the first transistors, the aligned is at an atomic level as would have been resulted from an epitaxial growth process.

A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.